diff options
| author | Owen Anderson <resistor@mac.com> | 2011-08-04 23:18:05 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-04 23:18:05 +0000 |
| commit | 14c903a76be7933cea746617d3f787fdf4de8203 (patch) | |
| tree | ba2ad9a70ebacc2c5ea1ce0c1d26fab1428f4800 /lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h | |
| parent | 039c2e19c4237fb484315a62e95222ac28640bb7 (diff) | |
| download | external_llvm-14c903a76be7933cea746617d3f787fdf4de8203.tar.gz external_llvm-14c903a76be7933cea746617d3f787fdf4de8203.tar.bz2 external_llvm-14c903a76be7933cea746617d3f787fdf4de8203.zip | |
Fix broken encodings for the Thumb2 LDRD/STRD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136942 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h | 23 |
1 files changed, 14 insertions, 9 deletions
diff --git a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h index 66a62ef5a5..a1b38f377a 100644 --- a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h +++ b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h @@ -1318,13 +1318,6 @@ static bool DisassembleThumb2LdStDual(MCInst &MI, unsigned Opcode, const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; if (!OpInfo) return false; - assert(NumOps >= 4 - && OpInfo[0].RegClass > 0 - && OpInfo[0].RegClass == OpInfo[1].RegClass - && OpInfo[2].RegClass > 0 - && OpInfo[3].RegClass < 0 - && "Expect >= 4 operands and first 3 as reg operands"); - // Thumnb allows for specifying Rt and Rt2, unlike ARM (which has Rt2==Rt+1). unsigned Rt = decodeRd(insn); unsigned Rt2 = decodeRs(insn); @@ -1357,20 +1350,32 @@ static bool DisassembleThumb2LdStDual(MCInst &MI, unsigned Opcode, // Add the <Rt> <Rt2> operands. unsigned RegClassPair = OpInfo[0].RegClass; unsigned RegClassBase = OpInfo[2].RegClass; - + MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassPair, decodeRd(insn)))); MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassPair, decodeRs(insn)))); MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassBase, decodeRn(insn)))); + unsigned Added = 4; + switch (MI.getOpcode()) { + case ARM::t2LDRD_PRE: + case ARM::t2LDRD_POST: + case ARM::t2STRD_PRE: + case ARM::t2STRD_POST: + MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassBase, + decodeRn(insn)))); + Added = 5; + default: + break; + } // Finally add (+/-)imm8*4, depending on the U bit. int Offset = getImm8(insn) * 4; if (getUBit(insn) == 0) Offset = -Offset; MI.addOperand(MCOperand::CreateImm(Offset)); - NumOpsAdded = 4; + NumOpsAdded = Added; return true; } |