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authorEvan Cheng <evan.cheng@apple.com>2006-11-27 23:37:22 +0000
committerEvan Cheng <evan.cheng@apple.com>2006-11-27 23:37:22 +0000
commitc0f64ffab93d11fb27a3b8a0707b77400918a20e (patch)
treecc2cfef30bfb1344f83d8cfd08aace72274bde47 /lib/Target/ARM/ARMInstrInfo.cpp
parent722a0cafbd47eb6b8bf9a9e9dce2f6cb8383fef1 (diff)
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Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
of opcode and number of operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31947 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrInfo.cpp')
-rw-r--r--lib/Target/ARM/ARMInstrInfo.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index beea31ca8e..f99615b572 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -19,7 +19,8 @@
using namespace llvm;
ARMInstrInfo::ARMInstrInfo()
- : TargetInstrInfo(ARMInsts, sizeof(ARMInsts)/sizeof(ARMInsts[0])) {
+ : TargetInstrInfo(ARMInsts, sizeof(ARMInsts)/sizeof(ARMInsts[0])),
+ RI(*this) {
}
const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
@@ -54,5 +55,5 @@ void ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
const std::vector<MachineOperand> &Cond)const{
// Can only insert uncond branches so far.
assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
- BuildMI(&MBB, ARM::b, 1).addMBB(TBB);
+ BuildMI(&MBB, get(ARM::b)).addMBB(TBB);
}