Teach bottom up pre-ra scheduler to track register pressure. Work in progress.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108991 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 30 insertions, 12 deletions

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index f6d25d8706..733042266d 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -550,20 +550,38 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
     benefitFromCodePlacementOpt = true;
 }
 
-const TargetRegisterClass *
-ARMTargetLowering::findRepresentativeClass(const TargetRegisterClass *RC) const{
-  switch (RC->getID()) {
+std::pair<const TargetRegisterClass*, uint8_t>
+ARMTargetLowering::findRepresentativeClass(EVT VT) const{
+  const TargetRegisterClass *RRC = 0;
+  uint8_t Cost = 1;
+  switch (VT.getSimpleVT().SimpleTy) {
   default:
-    return RC;
-  case ARM::tGPRRegClassID:
-  case ARM::GPRRegClassID:
-    return ARM::GPRRegisterClass;
-  case ARM::SPRRegClassID:
-  case ARM::DPRRegClassID:
-    return ARM::DPRRegisterClass;
-  case ARM::QPRRegClassID:
-    return ARM::QPRRegisterClass;
+    return TargetLowering::findRepresentativeClass(VT);
+  // Use SPR as representative register class for all floating point
+  // and vector types.
+  case MVT::f32:
+    RRC = ARM::SPRRegisterClass;
+    break;
+  case MVT::f64: case MVT::v8i8: case MVT::v4i16:
+  case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
+    RRC = ARM::SPRRegisterClass;
+    Cost = 2;
+    break;
+  case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
+  case MVT::v4f32: case MVT::v2f64:
+    RRC = ARM::SPRRegisterClass;
+    Cost = 4;
+    break;
+  case MVT::v4i64:
+    RRC = ARM::SPRRegisterClass;
+    Cost = 8;
+    break;
+  case MVT::v8i64:
+    RRC = ARM::SPRRegisterClass;
+    Cost = 16;
+    break;
   }
+  return std::make_pair(RRC, Cost);
 }
 
 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {