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authorBruno Cardoso Lopes <bruno.cardoso@gmail.com>2011-04-04 17:18:19 +0000
committerBruno Cardoso Lopes <bruno.cardoso@gmail.com>2011-04-04 17:18:19 +0000
commitac79e4c82f201c30a06c2cd05baebd20f5b49888 (patch)
tree7e7b27fc8910e9f11013439d325c37a5763f5833 /lib/Target/ARM/ARMAddressingModes.h
parent74a26fe099e27c60493b7493e47b1ad53ac333cd (diff)
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- Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT
also fix the encoding of the later. - Add a new encoding bit to describe the index mode used in AM3. - Teach printAddrMode3Operand to check by the addressing mode which index mode to print. - Testcases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128832 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMAddressingModes.h')
-rw-r--r--lib/Target/ARM/ARMAddressingModes.h13
1 files changed, 9 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMAddressingModes.h b/lib/Target/ARM/ARMAddressingModes.h
index 0b5fb1dd5d..595708fa78 100644
--- a/lib/Target/ARM/ARMAddressingModes.h
+++ b/lib/Target/ARM/ARMAddressingModes.h
@@ -409,7 +409,7 @@ namespace ARM_AM {
// The first operand is always a Reg. The second operand is a reg if in
// reg/reg form, otherwise it's reg#0. The third field encodes the operation
// in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The
- // forth operand 16-17 encodes the index mode.
+ // fourth operand 16-17 encodes the index mode.
//
// If this addressing mode is a frame index (before prolog/epilog insertion
// and code rewriting), this operand will have the form: FI#, reg0, <offs>
@@ -446,12 +446,14 @@ namespace ARM_AM {
//
// The first operand is always a Reg. The second operand is a reg if in
// reg/reg form, otherwise it's reg#0. The third field encodes the operation
- // in bit 8, the immediate in bits 0-7.
+ // in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the
+ // index mode.
/// getAM3Opc - This function encodes the addrmode3 opc field.
- static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset) {
+ static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset,
+ unsigned IdxMode = 0) {
bool isSub = Opc == sub;
- return ((int)isSub << 8) | Offset;
+ return ((int)isSub << 8) | Offset | (IdxMode << 9);
}
static inline unsigned char getAM3Offset(unsigned AM3Opc) {
return AM3Opc & 0xFF;
@@ -459,6 +461,9 @@ namespace ARM_AM {
static inline AddrOpc getAM3Op(unsigned AM3Opc) {
return ((AM3Opc >> 8) & 1) ? sub : add;
}
+ static inline unsigned getAM3IdxMode(unsigned AM3Opc) {
+ return (AM3Opc >> 9);
+ }
//===--------------------------------------------------------------------===//
// Addressing Mode #4