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authorDale Johannesen <dalej@apple.com>2009-10-28 21:56:18 +0000
committerDale Johannesen <dalej@apple.com>2009-10-28 21:56:18 +0000
commite841d2f8679f603ec453fe56a3bf9bea97aef303 (patch)
tree984e104f4adb8db09cf2edaf14916c983fe84367 /lib/CodeGen/VirtRegRewriter.cpp
parent7e5d2ff20fb4ca86b27f28fc5fb9d589bc0752fd (diff)
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When we generate spill code, then decide we don't need
to spill after all, we weren't handling 2-instruction spill sequences correctly (PPC Altivec). We need to remove the store in this case. Removing the other instruction(s) would be goodness but is not needed for correctness, and isn't done here. 7331562. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85437 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/VirtRegRewriter.cpp')
-rw-r--r--lib/CodeGen/VirtRegRewriter.cpp5
1 files changed, 4 insertions, 1 deletions
diff --git a/lib/CodeGen/VirtRegRewriter.cpp b/lib/CodeGen/VirtRegRewriter.cpp
index 107c19ad01..a9ff1ad9ae 100644
--- a/lib/CodeGen/VirtRegRewriter.cpp
+++ b/lib/CodeGen/VirtRegRewriter.cpp
@@ -1430,6 +1430,7 @@ private:
std::vector<MachineOperand*> &KillOps,
VirtRegMap &VRM) {
+ MachineBasicBlock::iterator oldNextMII = next(MII);
TII->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC);
MachineInstr *StoreMI = next(MII);
VRM.addSpillSlotUse(StackSlot, StoreMI);
@@ -1466,7 +1467,9 @@ private:
}
}
- LastStore = next(MII);
+ // Allow for multi-instruction spill sequences, as on PPC Altivec. Presume
+ // the last of multiple instructions is the actual store.
+ LastStore = prior(oldNextMII);
// If the stack slot value was previously available in some other
// register, change it now. Otherwise, make the register available,