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author | Mark Lacey <mark.lacey@apple.com> | 2013-08-14 23:50:04 +0000 |
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committer | Mark Lacey <mark.lacey@apple.com> | 2013-08-14 23:50:04 +0000 |
commit | 1feb5854aeeda897e9318c8193d187673c8576b8 (patch) | |
tree | c9d6537caa799bb43598d3744c5b4a54f9a0ceb9 /lib/CodeGen/RegAllocPBQP.cpp | |
parent | a41520cf9b9cefed2091a0624a34c5f7fdb42a68 (diff) | |
download | external_llvm-1feb5854aeeda897e9318c8193d187673c8576b8.tar.gz external_llvm-1feb5854aeeda897e9318c8193d187673c8576b8.tar.bz2 external_llvm-1feb5854aeeda897e9318c8193d187673c8576b8.zip |
Track new virtual registers by register number.
Track new virtual registers by register number, rather than by the live
interval created for them. This is the first step in separating the
creation of new virtual registers and new live intervals. Eventually
live intervals will be created and populated on demand after the virtual
registers have been created and used in instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188434 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocPBQP.cpp')
-rw-r--r-- | lib/CodeGen/RegAllocPBQP.cpp | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/lib/CodeGen/RegAllocPBQP.cpp b/lib/CodeGen/RegAllocPBQP.cpp index 81ecca1f2e..7786ecdf37 100644 --- a/lib/CodeGen/RegAllocPBQP.cpp +++ b/lib/CodeGen/RegAllocPBQP.cpp @@ -491,7 +491,7 @@ bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAProblem &problem, vrm->assignVirt2Phys(vreg, preg); } else if (problem.isSpillOption(vreg, alloc)) { vregsToAlloc.erase(vreg); - SmallVector<LiveInterval*, 8> newSpills; + SmallVector<unsigned, 8> newSpills; LiveRangeEdit LRE(&lis->getInterval(vreg), newSpills, *mf, *lis, vrm); spiller->spill(LRE); @@ -502,9 +502,10 @@ bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAProblem &problem, // allocate. for (LiveRangeEdit::iterator itr = LRE.begin(), end = LRE.end(); itr != end; ++itr) { - assert(!(*itr)->empty() && "Empty spill range."); - DEBUG(dbgs() << PrintReg((*itr)->reg, tri) << " "); - vregsToAlloc.insert((*itr)->reg); + LiveInterval &li = lis->getInterval(*itr); + assert(!li.empty() && "Empty spill range."); + DEBUG(dbgs() << PrintReg(li.reg, tri) << " "); + vregsToAlloc.insert(li.reg); } DEBUG(dbgs() << ")\n"); |