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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-03-16 22:56:08 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-03-16 22:56:08 +0000 |
| commit | c46570dc05851395829bef904bb6ddb1260400d1 (patch) | |
| tree | 179a2496f8f6beed6e7129a59a84a99c04760a6d /lib/CodeGen/RegAllocGreedy.cpp | |
| parent | ebe8173941238cfbabadb1c63bca7fb7dcf2adbe (diff) | |
| download | external_llvm-c46570dc05851395829bef904bb6ddb1260400d1.tar.gz external_llvm-c46570dc05851395829bef904bb6ddb1260400d1.tar.bz2 external_llvm-c46570dc05851395829bef904bb6ddb1260400d1.zip | |
Clarify debugging output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127771 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocGreedy.cpp')
| -rw-r--r-- | lib/CodeGen/RegAllocGreedy.cpp | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp index 57119aacd2..940ed81465 100644 --- a/lib/CodeGen/RegAllocGreedy.cpp +++ b/lib/CodeGen/RegAllocGreedy.cpp @@ -646,7 +646,9 @@ void RAGreedy::splitAroundRegion(LiveInterval &VirtReg, unsigned PhysReg, IndexPair &IP = InterferenceRanges[i]; DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " -> EB#" << Bundles->getBundle(BI.MBB->getNumber(), 1) - << " intf [" << IP.first << ';' << IP.second << ')'); + << " [" << BI.Start << ';' << BI.LastSplitPoint << '-' + << BI.Stop << ") intf [" << IP.first << ';' << IP.second + << ')'); // The interference interval should either be invalid or overlap MBB. assert((!IP.first.isValid() || IP.first < BI.Stop) && "Bad interference"); @@ -741,7 +743,8 @@ void RAGreedy::splitAroundRegion(LiveInterval &VirtReg, unsigned PhysReg, IndexPair &IP = InterferenceRanges[i]; DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0) - << " -> BB#" << BI.MBB->getNumber()); + << " -> BB#" << BI.MBB->getNumber() << " [" << BI.Start << ';' + << BI.LastSplitPoint << '-' << BI.Stop << ')'); // Check interference entering the block. if (!IP.first.isValid()) { @@ -1266,6 +1269,9 @@ unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg, LiveRangeEdit LRE(VirtReg, NewVRegs, this); spiller().spill(LRE); + if (VerifyEnabled) + MF->verify(this, "After spilling"); + // The live virtual register requesting allocation was spilled, so tell // the caller not to allocate anything during this round. return 0; |