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author | Stephen Hines <srhines@google.com> | 2014-04-25 20:47:46 +0000 |
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committer | Gerrit Code Review <noreply-gerritcodereview@google.com> | 2014-04-25 20:47:46 +0000 |
commit | 37a6adeb1525309c655d8acb341019d475b2a6a5 (patch) | |
tree | e6cfb69fbbd937f450eeb83bfb83b9da3b01275a /lib/CodeGen/RegAllocBase.cpp | |
parent | 69a8640022b04415ae9fac62f8ab090601d8f889 (diff) | |
parent | 36b56886974eae4f9c5ebc96befd3e7bfe5de338 (diff) | |
download | external_llvm-37a6adeb1525309c655d8acb341019d475b2a6a5.tar.gz external_llvm-37a6adeb1525309c655d8acb341019d475b2a6a5.tar.bz2 external_llvm-37a6adeb1525309c655d8acb341019d475b2a6a5.zip |
Merge "Update to LLVM 3.5a."
Diffstat (limited to 'lib/CodeGen/RegAllocBase.cpp')
-rw-r--r-- | lib/CodeGen/RegAllocBase.cpp | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/lib/CodeGen/RegAllocBase.cpp b/lib/CodeGen/RegAllocBase.cpp index 293e306a29..33584f8680 100644 --- a/lib/CodeGen/RegAllocBase.cpp +++ b/lib/CodeGen/RegAllocBase.cpp @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// This file defines the RegAllocBase class which provides comon functionality +// This file defines the RegAllocBase class which provides common functionality // for LiveIntervalUnion-based register allocators. // //===----------------------------------------------------------------------===// @@ -101,8 +101,8 @@ void RegAllocBase::allocatePhysRegs() { // register if possible and populate a list of new live intervals that // result from splitting. DEBUG(dbgs() << "\nselectOrSplit " - << MRI->getRegClass(VirtReg->reg)->getName() - << ':' << *VirtReg << '\n'); + << MRI->getRegClass(VirtReg->reg)->getName() + << ':' << *VirtReg << " w=" << VirtReg->weight << '\n'); typedef SmallVector<unsigned, 4> VirtRegVec; VirtRegVec SplitVRegs; unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs); @@ -110,11 +110,16 @@ void RegAllocBase::allocatePhysRegs() { if (AvailablePhysReg == ~0u) { // selectOrSplit failed to find a register! // Probably caused by an inline asm. - MachineInstr *MI; - for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(VirtReg->reg); - (MI = I.skipInstruction());) - if (MI->isInlineAsm()) + MachineInstr *MI = 0; + for (MachineRegisterInfo::reg_instr_iterator + I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end(); + I != E; ) { + MachineInstr *TmpMI = &*(I++); + if (TmpMI->isInlineAsm()) { + MI = TmpMI; break; + } + } if (MI) MI->emitError("inline assembly requires more registers than available"); else |