Next round of earlyclobber handling. Approach the

RA problem by expanding the live interval of an
earlyclobber def back one slot.  Remove
overlap-earlyclobber throughout.  Remove 
earlyclobber bits and their handling from
live internals.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56539 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 1 insertions, 20 deletions

diff --git a/include/llvm/CodeGen/MachineOperand.h b/include/llvm/CodeGen/MachineOperand.h
index c2399beaf6..40876dbfca 100644
--- a/include/llvm/CodeGen/MachineOperand.h
+++ b/include/llvm/CodeGen/MachineOperand.h
@@ -73,12 +73,6 @@ private:
   /// model the GCC inline asm '&' constraint modifier.
   bool IsEarlyClobber : 1;
 
-  /// OverlapsEarlyClobber - True if this MO_Register operand is used as an
-  /// input to an inline asm that has the earlyclobber bit set on some other
-  /// operand.  Flag is not valid for any other case.   See gcc doc
-  /// for description of earlyclobber.
-  bool OverlapsEarlyClobber : 1;
-
   /// SubReg - Subregister number, only valid for MO_Register.  A value of 0
   /// indicates the MO_Register has no subReg.
   unsigned char SubReg;
@@ -188,11 +182,6 @@ public:
     return IsEarlyClobber;
   }
 
-  bool overlapsEarlyClobber() const {
-    assert(isRegister() && "Wrong MachineOperand accessor");
-    return OverlapsEarlyClobber;
-  }
-
   /// getNextOperandForReg - Return the next MachineOperand in the function that
   /// uses or defines this register.
   MachineOperand *getNextOperandForReg() const {
@@ -243,11 +232,6 @@ public:
     IsEarlyClobber = Val;
   }
 
-  void setOverlapsEarlyClobber(bool Val = true) {
-    assert(isRegister() && "Wrong MachineOperand accessor");
-    OverlapsEarlyClobber = Val;
-  }
-
   //===--------------------------------------------------------------------===//
   // Accessors for various operand types.
   //===--------------------------------------------------------------------===//
@@ -353,15 +337,13 @@ public:
   static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
                                   bool isKill = false, bool isDead = false,
                                   unsigned SubReg = 0,
-                                  bool isEarlyClobber = false,
-                                  bool overlapsEarlyClobber = false) {
+                                  bool isEarlyClobber = false) {
     MachineOperand Op(MachineOperand::MO_Register);
     Op.IsDef = isDef;
     Op.IsImp = isImp;
     Op.IsKill = isKill;
     Op.IsDead = isDead;
     Op.IsEarlyClobber = isEarlyClobber;
-    Op.OverlapsEarlyClobber = overlapsEarlyClobber;
     Op.Contents.Reg.RegNo = Reg;
     Op.Contents.Reg.Prev = 0;
     Op.Contents.Reg.Next = 0;
@@ -408,7 +390,6 @@ public:
     IsKill   = MO.IsKill;
     IsDead   = MO.IsDead;
     IsEarlyClobber = MO.IsEarlyClobber;
-    OverlapsEarlyClobber = MO.OverlapsEarlyClobber;
     SubReg   = MO.SubReg;
     ParentMI = MO.ParentMI;
     Contents = MO.Contents;