diff options
| author | Chris Lattner <sabre@nondot.org> | 2010-02-11 08:45:56 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2010-02-11 08:45:56 +0000 |
| commit | ecfb3c3d665480e04c051b4b229607768612d28d (patch) | |
| tree | e95660b1aa2600ce210f695d6b568aacf8b0f6b6 | |
| parent | 5526b699014b0b58e08d7d43e28084589eda26f2 (diff) | |
| download | external_llvm-ecfb3c3d665480e04c051b4b229607768612d28d.tar.gz external_llvm-ecfb3c3d665480e04c051b4b229607768612d28d.tar.bz2 external_llvm-ecfb3c3d665480e04c051b4b229607768612d28d.zip | |
dont' call getX86RegNum on X86::RIP, it doesn't like that. This
fixes the remaining x86-64 jit failures afaik.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95867 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86CodeEmitter.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/X86/X86MCCodeEmitter.cpp | 6 |
2 files changed, 7 insertions, 3 deletions
diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index bcf3f15d42..6d5fa8da0d 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -387,7 +387,9 @@ void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI, // If no BaseReg, issue a RIP relative instruction only if the MCE can // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table // 2-7) and absolute references. - unsigned BaseRegNo = BaseReg != 0 ? getX86RegNum(BaseReg) : -1U; + unsigned BaseRegNo = -1U; + if (BaseReg != 0 && BaseReg != X86::RIP) + BaseRegNo = getX86RegNum(BaseReg); if (// The SIB byte must be used if there is an index register. IndexReg.getReg() == 0 && diff --git a/lib/Target/X86/X86MCCodeEmitter.cpp b/lib/Target/X86/X86MCCodeEmitter.cpp index ef1733f993..ba1bdc7851 100644 --- a/lib/Target/X86/X86MCCodeEmitter.cpp +++ b/lib/Target/X86/X86MCCodeEmitter.cpp @@ -175,8 +175,10 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op, const MCOperand &Scale = MI.getOperand(Op+1); const MCOperand &IndexReg = MI.getOperand(Op+2); unsigned BaseReg = Base.getReg(); - unsigned BaseRegNo = BaseReg != 0 ? GetX86RegNum(Base) : -1U; - + unsigned BaseRegNo = -1U; + if (BaseReg != 0 && BaseReg != X86::RIP) + BaseRegNo = GetX86RegNum(Base); + // Determine whether a SIB byte is needed. // If no BaseReg, issue a RIP relative instruction only if the MCE can // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table |