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| author | Jim Grosbach <grosbach@apple.com> | 2011-11-14 23:32:59 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-11-14 23:32:59 +0000 |
| commit | e052b9afa1301419f8b52eed9ed370393fcad78d (patch) | |
| tree | a3ed8dfd694fec3f09d0da0a408c6de0fe94a5d7 | |
| parent | 04db7f7a7d5d9312d2e40032883b708e321d55b3 (diff) | |
| download | external_llvm-e052b9afa1301419f8b52eed9ed370393fcad78d.tar.gz external_llvm-e052b9afa1301419f8b52eed9ed370393fcad78d.tar.bz2 external_llvm-e052b9afa1301419f8b52eed9ed370393fcad78d.zip | |
ARM parsing datatype suffix variants for non-writeback VLD1 instructions.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144592 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 41 | ||||
| -rw-r--r-- | test/MC/ARM/neon-vld-encoding.s | 28 |
2 files changed, 69 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index ce93beaa32..84747370ea 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -5198,3 +5198,44 @@ defm : VFPDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm", (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>; defm : VFPDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm", (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>; + +// VLD1 requires a size suffix, but also accepts type specific variants. +// Load one D register. +defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn", + (VLD1d8 VecListOneD:$Vd, addrmode6:$Rn, pred:$p)>; +defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn", + (VLD1d16 VecListOneD:$Vd, addrmode6:$Rn, pred:$p)>; +defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn", + (VLD1d32 VecListOneD:$Vd, addrmode6:$Rn, pred:$p)>; +defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn", + (VLD1d64 VecListOneD:$Vd, addrmode6:$Rn, pred:$p)>; + +// Load two D registers. +defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn", + (VLD1q8 VecListTwoD:$Vd, addrmode6:$Rn, pred:$p)>; +defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn", + (VLD1q16 VecListTwoD:$Vd, addrmode6:$Rn, pred:$p)>; +defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn", + (VLD1q32 VecListTwoD:$Vd, addrmode6:$Rn, pred:$p)>; +defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn", + (VLD1q64 VecListTwoD:$Vd, addrmode6:$Rn, pred:$p)>; + +// Load three D registers. +defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn", + (VLD1d8T VecListThreeD:$Vd, addrmode6:$Rn, pred:$p)>; +defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn", + (VLD1d16T VecListThreeD:$Vd, addrmode6:$Rn, pred:$p)>; +defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn", + (VLD1d32T VecListThreeD:$Vd, addrmode6:$Rn, pred:$p)>; +defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn", + (VLD1d64T VecListThreeD:$Vd, addrmode6:$Rn, pred:$p)>; + +// Load four D registers. +defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn", + (VLD1d8Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>; +defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn", + (VLD1d16Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>; +defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn", + (VLD1d32Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>; +defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn", + (VLD1d64Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>; diff --git a/test/MC/ARM/neon-vld-encoding.s b/test/MC/ARM/neon-vld-encoding.s index 6577b2d2ed..03a3cea37c 100644 --- a/test/MC/ARM/neon-vld-encoding.s +++ b/test/MC/ARM/neon-vld-encoding.s @@ -223,3 +223,31 @@ @ CHECK: vld1.8 {d6, d7}, [r9] @ encoding: [0x0f,0x6a,0x29,0xf4] @ CHECK: vld1.8 {d6, d7, d8, d9}, [r9] @ encoding: [0x0f,0x62,0x29,0xf4] + + +@ Spot-check additional size-suffix aliases. + vld1.8 {d2}, [r2] + vld1.p8 {d2}, [r2] + vld1.u8 {d2}, [r2] + + vld1.8 {q2}, [r2] + vld1.p8 {q2}, [r2] + vld1.u8 {q2}, [r2] + vld1.f32 {q2}, [r2] + + vld1.u8 {d2, d3, d4}, [r2] + vld1.i32 {d2, d3, d4}, [r2] + vld1.f64 {d2, d3, d4}, [r2] + +@ CHECK: vld1.8 {d2}, [r2] @ encoding: [0x0f,0x27,0x22,0xf4] +@ CHECK: vld1.8 {d2}, [r2] @ encoding: [0x0f,0x27,0x22,0xf4] +@ CHECK: vld1.8 {d2}, [r2] @ encoding: [0x0f,0x27,0x22,0xf4] + +@ CHECK: vld1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x22,0xf4] +@ CHECK: vld1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x22,0xf4] +@ CHECK: vld1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x22,0xf4] +@ CHECK: vld1.32 {d4, d5}, [r2] @ encoding: [0x8f,0x4a,0x22,0xf4] + +@ CHECK: vld1.8 {d2, d3, d4}, [r2] @ encoding: [0x0f,0x26,0x22,0xf4] +@ CHECK: vld1.32 {d2, d3, d4}, [r2] @ encoding: [0x8f,0x26,0x22,0xf4] +@ CHECK: vld1.64 {d2, d3, d4}, [r2] @ encoding: [0xcf,0x26,0x22,0xf4] |