diff options
| author | Rafael Espindola <rafael.espindola@gmail.com> | 2013-07-26 13:18:16 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2013-07-26 13:18:16 +0000 |
| commit | c735c1c2aed2cbaeb61296f4269535b5d13d8b0a (patch) | |
| tree | 7882359e4627974b53ac954fb9b7fa535278a4c2 | |
| parent | 5a24ed951b7f5e553a7e4e1415da5be247db443e (diff) | |
| download | external_llvm-c735c1c2aed2cbaeb61296f4269535b5d13d8b0a.tar.gz external_llvm-c735c1c2aed2cbaeb61296f4269535b5d13d8b0a.tar.bz2 external_llvm-c735c1c2aed2cbaeb61296f4269535b5d13d8b0a.zip | |
Revert "Add a target legalize hook for SplitVectorOperand"
This reverts commit 187198. It broke the bots.
The soft float test probably needs a -triple because of name differences.
On the hard float test I am getting a "roundss $1, %xmm0, %xmm0", instead of
"vroundss $1, %xmm0, %xmm0, %xmm0".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187201 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 2 | ||||
| -rw-r--r-- | test/CodeGen/NVPTX/vector-stores.ll | 30 | ||||
| -rw-r--r-- | test/CodeGen/X86/floor-soft-float.ll | 11 |
4 files changed, 1 insertions, 46 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 72c16b5d39..75bb6094f5 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -1031,10 +1031,6 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) { dbgs() << "\n"); SDValue Res = SDValue(); - // See if the target wants to custom split this node. - if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) - return false; - if (Res.getNode() == 0) { switch (N->getOpcode()) { default: diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index ad2d30891e..e75781e6ba 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -996,7 +996,7 @@ void X86TargetLowering::resetOperationActions() { setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal); } - if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) { + if (Subtarget->hasSSE41()) { setOperationAction(ISD::FFLOOR, MVT::f32, Legal); setOperationAction(ISD::FCEIL, MVT::f32, Legal); setOperationAction(ISD::FTRUNC, MVT::f32, Legal); diff --git a/test/CodeGen/NVPTX/vector-stores.ll b/test/CodeGen/NVPTX/vector-stores.ll deleted file mode 100644 index 49418122da..0000000000 --- a/test/CodeGen/NVPTX/vector-stores.ll +++ /dev/null @@ -1,30 +0,0 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s - -; CHECK: .visible .func foo1 -; CHECK: st.v2.f32 -define void @foo1(<2 x float> %val, <2 x float>* %ptr) { - store <2 x float> %val, <2 x float>* %ptr - ret void -} - -; CHECK: .visible .func foo2 -; CHECK: st.v4.f32 -define void @foo2(<4 x float> %val, <4 x float>* %ptr) { - store <4 x float> %val, <4 x float>* %ptr - ret void -} - -; CHECK: .visible .func foo3 -; CHECK: st.v2.u32 -define void @foo3(<2 x i32> %val, <2 x i32>* %ptr) { - store <2 x i32> %val, <2 x i32>* %ptr - ret void -} - -; CHECK: .visible .func foo4 -; CHECK: st.v4.u32 -define void @foo4(<4 x i32> %val, <4 x i32>* %ptr) { - store <4 x i32> %val, <4 x i32>* %ptr - ret void -} - diff --git a/test/CodeGen/X86/floor-soft-float.ll b/test/CodeGen/X86/floor-soft-float.ll deleted file mode 100644 index 158a82413d..0000000000 --- a/test/CodeGen/X86/floor-soft-float.ll +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: llc < %s -march=x86-64 -mattr=+sse41 -soft-float=0 | FileCheck %s --check-prefix=CHECK-HARD-FLOAT -; RUN: llc < %s -march=x86-64 -mattr=+sse41 -soft-float=1 | FileCheck %s --check-prefix=CHECK-SOFT-FLOAT - -declare float @llvm.floor.f32(float) - -; CHECK-SOFT-FLOAT: callq _floorf -; CHECK-HARD-FLOAT: vroundss $1, %xmm0, %xmm0, %xmm0 -define float @myfloor(float %a) { - %val = tail call float @llvm.floor.f32(float %a) - ret float %val -} |