aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorMichael Liao <michael.liao@intel.com>2012-09-17 18:05:20 +0000
committerMichael Liao <michael.liao@intel.com>2012-09-17 18:05:20 +0000
commitbb7300224738e65f9a9945dc7df2f360b1d4feb6 (patch)
tree1d80227c92012a41ce588ac204430262fdda3e5b
parent9bb938c5401db90817d16b32fa078066fb586551 (diff)
downloadexternal_llvm-bb7300224738e65f9a9945dc7df2f360b1d4feb6.tar.gz
external_llvm-bb7300224738e65f9a9945dc7df2f360b1d4feb6.tar.bz2
external_llvm-bb7300224738e65f9a9945dc7df2f360b1d4feb6.zip
Fix PR13859
- Preserve the original NOutVT during casting from vector to integer by extracting vector elements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164042 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp13
-rw-r--r--test/CodeGen/X86/pr13859.ll28
2 files changed, 35 insertions, 6 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
index 08668e1b40..7b8f138a34 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
@@ -95,17 +95,18 @@ void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
// Handle cases like i64 = BITCAST v1i64 on x86, where the operand
// is legal but the result is not.
unsigned NumElems = 2;
- EVT NVT = EVT::getVectorVT(*DAG.getContext(), NOutVT, NumElems);
+ EVT ElemVT = NOutVT;
+ EVT NVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, NumElems);
- // If <NOutVT * N> is not a legal type, try <NOutVT/2 * (N*2)>.
+ // If <ElemVT * N> is not a legal type, try <ElemVT/2 * (N*2)>.
while (!isTypeLegal(NVT)) {
- unsigned NewSizeInBits = NOutVT.getSizeInBits() / 2;
+ unsigned NewSizeInBits = ElemVT.getSizeInBits() / 2;
// If the element size is smaller than byte, bail.
if (NewSizeInBits < 8)
break;
NumElems *= 2;
- NOutVT = EVT::getIntegerVT(*DAG.getContext(), NewSizeInBits);
- NVT = EVT::getVectorVT(*DAG.getContext(), NOutVT, NumElems);
+ ElemVT = EVT::getIntegerVT(*DAG.getContext(), NewSizeInBits);
+ NVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, NumElems);
}
if (isTypeLegal(NVT)) {
@@ -113,7 +114,7 @@ void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
SmallVector<SDValue, 8> Vals;
for (unsigned i = 0; i < NumElems; ++i)
- Vals.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NOutVT,
+ Vals.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ElemVT,
CastInOp, DAG.getIntPtrConstant(i)));
// Build Lo, Hi pair by pairing extracted elements if needed.
diff --git a/test/CodeGen/X86/pr13859.ll b/test/CodeGen/X86/pr13859.ll
new file mode 100644
index 0000000000..719721dfd8
--- /dev/null
+++ b/test/CodeGen/X86/pr13859.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32-S128"
+target triple = "i386-apple-macosx10.7.0"
+
+define void @_Z17FilterYUVRows_MMXi(i32 %af) nounwind ssp {
+entry:
+ %aMyAlloca = alloca i32, align 32
+ %dest = alloca <1 x i64>, align 32
+
+ %a32 = load i32* %aMyAlloca, align 4
+ %aconv = trunc i32 %a32 to i16
+ %a36 = insertelement <4 x i16> undef, i16 %aconv, i32 0
+ %a37 = insertelement <4 x i16> %a36, i16 %aconv, i32 1
+ %a38 = insertelement <4 x i16> %a37, i16 %aconv, i32 2
+ %a39 = insertelement <4 x i16> %a38, i16 %aconv, i32 3
+ %a40 = bitcast <4 x i16> %a39 to x86_mmx
+ %a41 = bitcast x86_mmx %a40 to <1 x i64>
+
+ %a47 = trunc i32 %a32 to i1
+ br i1 %a47, label %a48, label %a49
+
+a48:
+ unreachable
+
+a49:
+ store <1 x i64> %a41, <1 x i64>* %dest, align 8 ; !!!
+ ret void
+}