diff options
| author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-14 22:22:09 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-14 22:22:09 +0000 |
| commit | a7b7ab32998f6a643b63e7a82cf98c3498960d90 (patch) | |
| tree | c5e8f347d886d864cbfb8bd447683b9228b34a58 | |
| parent | 9735dc6c1b20ae311bba50fbf28feb8c41810d3c (diff) | |
| download | external_llvm-a7b7ab32998f6a643b63e7a82cf98c3498960d90.tar.gz external_llvm-a7b7ab32998f6a643b63e7a82cf98c3498960d90.tar.bz2 external_llvm-a7b7ab32998f6a643b63e7a82cf98c3498960d90.zip | |
R600/SI: Allow conversion between v32i8 and v8i32
Patch by: Marek Olšák
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188420 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/R600/SIInstructions.td | 5 | ||||
| -rw-r--r-- | lib/Target/R600/SIRegisterInfo.td | 4 | ||||
| -rw-r--r-- | test/CodeGen/R600/bitcast.ll | 21 |
3 files changed, 28 insertions, 2 deletions
diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index 7393e1de56..82c4b5e9d3 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -1510,6 +1510,11 @@ def : BitConvert <v2i32, v2f32, VReg_64>; def : BitConvert <v4f32, v4i32, VReg_128>; def : BitConvert <v4i32, v4f32, VReg_128>; +def : BitConvert <v8i32, v32i8, SReg_256>; +def : BitConvert <v32i8, v8i32, SReg_256>; +def : BitConvert <v8i32, v32i8, VReg_256>; +def : BitConvert <v32i8, v8i32, VReg_256>; + /********** =================== **********/ /********** Src & Dst modifiers **********/ /********** =================== **********/ diff --git a/lib/Target/R600/SIRegisterInfo.td b/lib/Target/R600/SIRegisterInfo.td index 292b9d23db..82d1e71925 100644 --- a/lib/Target/R600/SIRegisterInfo.td +++ b/lib/Target/R600/SIRegisterInfo.td @@ -159,7 +159,7 @@ def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, i1], 64, def SReg_128 : RegisterClass<"AMDGPU", [v16i8, i128], 128, (add SGPR_128)>; -def SReg_256 : RegisterClass<"AMDGPU", [v32i8], 256, (add SGPR_256)>; +def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add SGPR_256)>; def SReg_512 : RegisterClass<"AMDGPU", [v64i8], 512, (add SGPR_512)>; @@ -174,7 +174,7 @@ def VReg_96 : RegisterClass<"AMDGPU", [untyped], 96, (add VGPR_96)> { def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32], 128, (add VGPR_128)>; -def VReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 256, (add VGPR_256)>; +def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add VGPR_256)>; def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>; diff --git a/test/CodeGen/R600/bitcast.ll b/test/CodeGen/R600/bitcast.ll new file mode 100644 index 0000000000..399444bb09 --- /dev/null +++ b/test/CodeGen/R600/bitcast.ll @@ -0,0 +1,21 @@ +; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s + +; This test just checks that the compiler doesn't crash. +; CHECK-LABEL: @v32i8_to_v8i32 +; CHECK: S_ENDPGM + +define void @v32i8_to_v8i32(<32 x i8> addrspace(2)* inreg) #0 { +entry: + %1 = load <32 x i8> addrspace(2)* %0 + %2 = bitcast <32 x i8> %1 to <8 x i32> + %3 = extractelement <8 x i32> %2, i32 1 + %4 = icmp ne i32 %3, 0 + %5 = select i1 %4, float 0.0, float 1.0 + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %5, float %5, float %5, float %5) + ret void +} + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) + +attributes #0 = { "ShaderType"="0" } + |