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| author | Bill Wendling <isanbard@gmail.com> | 2013-05-30 00:32:04 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2013-05-30 00:32:04 +0000 |
| commit | 8a65e11c9fdfd86d6b9a6b365afcbafddd97a6f3 (patch) | |
| tree | 86d47ac237fd2fed4276190ba375ae11ff7b05cf | |
| parent | 3b7f3b1434bd5fe973000a14e4cf052f7cbcc41e (diff) | |
| download | external_llvm-8a65e11c9fdfd86d6b9a6b365afcbafddd97a6f3.tar.gz external_llvm-8a65e11c9fdfd86d6b9a6b365afcbafddd97a6f3.tar.bz2 external_llvm-8a65e11c9fdfd86d6b9a6b365afcbafddd97a6f3.zip | |
This testcase tests command line attributes which we don't yet support.
In fact, we're probably going to support these flags in completely different
ways. So this test is no longer valid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182899 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | test/CodeGen/X86/subtarget-feature-change.ll | 62 |
1 files changed, 0 insertions, 62 deletions
diff --git a/test/CodeGen/X86/subtarget-feature-change.ll b/test/CodeGen/X86/subtarget-feature-change.ll deleted file mode 100644 index 04d4a71996..0000000000 --- a/test/CodeGen/X86/subtarget-feature-change.ll +++ /dev/null @@ -1,62 +0,0 @@ -; RUN: llc < %s -march=x86-64 | FileCheck %s - -; This should not generate SSE instructions: -; -; CHECK: without.sse: -; CHECK: flds -; CHECK: fmuls -; CHECK: fstps -define void @without.sse(float* nocapture %a, float* nocapture %b, float* nocapture %c, i32 %n) #0 { -entry: - %cmp9 = icmp sgt i32 %n, 0 - br i1 %cmp9, label %for.body, label %for.end - -for.body: - %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] - %arrayidx = getelementptr inbounds float* %b, i64 %indvars.iv - %0 = load float* %arrayidx, align 4 - %arrayidx2 = getelementptr inbounds float* %c, i64 %indvars.iv - %1 = load float* %arrayidx2, align 4 - %mul = fmul float %0, %1 - %arrayidx4 = getelementptr inbounds float* %a, i64 %indvars.iv - store float %mul, float* %arrayidx4, align 4 - %indvars.iv.next = add i64 %indvars.iv, 1 - %lftr.wideiv = trunc i64 %indvars.iv.next to i32 - %exitcond = icmp eq i32 %lftr.wideiv, %n - br i1 %exitcond, label %for.end, label %for.body - -for.end: - ret void -} - -; This should generate SSE instructions: -; -; CHECK: with.sse -; CHECK: movss -; CHECK: mulss -; CHECK: movss -define void @with.sse(float* nocapture %a, float* nocapture %b, float* nocapture %c, i32 %n) #1 { -entry: - %cmp9 = icmp sgt i32 %n, 0 - br i1 %cmp9, label %for.body, label %for.end - -for.body: - %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] - %arrayidx = getelementptr inbounds float* %b, i64 %indvars.iv - %0 = load float* %arrayidx, align 4 - %arrayidx2 = getelementptr inbounds float* %c, i64 %indvars.iv - %1 = load float* %arrayidx2, align 4 - %mul = fmul float %0, %1 - %arrayidx4 = getelementptr inbounds float* %a, i64 %indvars.iv - store float %mul, float* %arrayidx4, align 4 - %indvars.iv.next = add i64 %indvars.iv, 1 - %lftr.wideiv = trunc i64 %indvars.iv.next to i32 - %exitcond = icmp eq i32 %lftr.wideiv, %n - br i1 %exitcond, label %for.end, label %for.body - -for.end: - ret void -} - -attributes #0 = { nounwind optsize ssp uwtable "target-cpu"="core2" "target-features"="-sse4a,-avx2,-xop,-fma4,-bmi2,-3dnow,-3dnowa,-pclmul,-sse,-avx,-sse41,-ssse3,+mmx,-rtm,-sse42,-lzcnt,-f16c,-popcnt,-bmi,-aes,-fma,-rdrand,-sse2,-sse3" } -attributes #1 = { nounwind optsize ssp uwtable "target-cpu"="core2" "target-features"="-sse4a,-avx2,-xop,-fma4,-bmi2,-3dnow,-3dnowa,-pclmul,+sse,-avx,-sse41,+ssse3,+mmx,-rtm,-sse42,-lzcnt,-f16c,-popcnt,-bmi,-aes,-fma,-rdrand,+sse2,+sse3" } |