Change createPostRAScheduler so it can be turned off at llc -O1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84273 91177308-0d34-0410-b5e6-96231b3b80d8

6 files changed, 31 insertions, 14 deletions

diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h
index 1e7115e090..d0d610370b 100644
--- a/include/llvm/CodeGen/Passes.h
+++ b/include/llvm/CodeGen/Passes.h
@@ -15,13 +15,13 @@
 #ifndef LLVM_CODEGEN_PASSES_H
 #define LLVM_CODEGEN_PASSES_H
 
+#include "llvm/Target/TargetMachine.h"
 #include <string>
 
 namespace llvm {
 
   class FunctionPass;
   class PassInfo;
-  class TargetMachine;
   class TargetLowering;
   class RegisterCoalescer;
   class raw_ostream;
@@ -119,8 +119,9 @@ namespace llvm {
   ///
   FunctionPass *createLowerSubregsPass();
 
-  /// createPostRAScheduler - under development.
-  FunctionPass *createPostRAScheduler();
+  /// createPostRAScheduler - This pass performs post register allocation
+  /// scheduling.
+  FunctionPass *createPostRAScheduler(CodeGenOpt::Level OptLevel);
 
   /// BranchFolding Pass - This pass performs machine code CFG based
   /// optimizations to delete branches to branches, eliminate branches to
diff --git a/include/llvm/Target/TargetSubtarget.h b/include/llvm/Target/TargetSubtarget.h
index ac094f6644..5edb86f770 100644
--- a/include/llvm/Target/TargetSubtarget.h
+++ b/include/llvm/Target/TargetSubtarget.h
@@ -14,6 +14,8 @@
 #ifndef LLVM_TARGET_TARGETSUBTARGET_H
 #define LLVM_TARGET_TARGETSUBTARGET_H
 
+#include "llvm/Target/TargetMachine.h"
+
 namespace llvm {
 
 class SDep;
@@ -39,9 +41,12 @@ public:
   /// should be attempted.
   virtual unsigned getSpecialAddressLatency() const { return 0; }
 
-  // enablePostRAScheduler - Return true to enable
-  // post-register-allocation scheduling.
-  virtual bool enablePostRAScheduler() const { return false; }
+  // enablePostRAScheduler - If the target can benefit from post-regalloc
+  // scheduling and the specified optimization level meets the requirement
+  // return true to enable post-register-allocation scheduling.
+  virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
+    return false;
+  }
 
   // adjustSchedDependency - Perform target specific adjustments to
   // the latency of a schedule dependency.
diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp
index 4e713a6ed3..e58a9ca82c 100644
--- a/lib/CodeGen/LLVMTargetMachine.cpp
+++ b/lib/CodeGen/LLVMTargetMachine.cpp
@@ -323,7 +323,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
 
   // Second pass scheduler.
   if (OptLevel != CodeGenOpt::None) {
-    PM.add(createPostRAScheduler());
+    PM.add(createPostRAScheduler(OptLevel));
     printAndVerify(PM);
   }
 
diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp
index 706f5f2df0..4da5496c07 100644
--- a/lib/CodeGen/PostRASchedulerList.cpp
+++ b/lib/CodeGen/PostRASchedulerList.cpp
@@ -78,10 +78,12 @@ DebugMod("postra-sched-debugmod",
 namespace {
   class VISIBILITY_HIDDEN PostRAScheduler : public MachineFunctionPass {
     AliasAnalysis *AA;
+    CodeGenOpt::Level OptLevel;
 
   public:
     static char ID;
-    PostRAScheduler() : MachineFunctionPass(&ID) {}
+    PostRAScheduler(CodeGenOpt::Level ol) :
+      MachineFunctionPass(&ID), OptLevel(ol) {}
 
     void getAnalysisUsage(AnalysisUsage &AU) const {
       AU.setPreservesCFG();
@@ -238,7 +240,7 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
   } else {
     // Check that post-RA scheduling is enabled for this target.
     const TargetSubtarget &ST = Fn.getTarget().getSubtarget<TargetSubtarget>();
-    if (!ST.enablePostRAScheduler())
+    if (!ST.enablePostRAScheduler(OptLevel))
       return false;
   }
 
@@ -1195,6 +1197,6 @@ void SchedulePostRATDList::ListScheduleTopDown() {
 //                         Public Constructor Functions
 //===----------------------------------------------------------------------===//
 
-FunctionPass *llvm::createPostRAScheduler() {
-  return new PostRAScheduler();
+FunctionPass *llvm::createPostRAScheduler(CodeGenOpt::Level OptLevel) {
+  return new PostRAScheduler(OptLevel);
 }
diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h
index 7098fd4f36..bc5768e63a 100644
--- a/lib/Target/ARM/ARMSubtarget.h
+++ b/lib/Target/ARM/ARMSubtarget.h
@@ -126,9 +126,11 @@ protected:
 
   const std::string & getCPUString() const { return CPUString; }
   
-  /// enablePostRAScheduler - From TargetSubtarget, return true to
-  /// enable post-RA scheduler.
-  bool enablePostRAScheduler() const { return PostRAScheduler; }
+  /// enablePostRAScheduler - True at 'More' optimization except
+  /// for Thumb1.
+  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
+    return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
+  }
 
   /// getInstrItins - Return the instruction itineraies based on subtarget
   /// selection.
diff --git a/lib/Target/X86/X86Subtarget.h b/lib/Target/X86/X86Subtarget.h
index cb14e3c965..16a2f1023c 100644
--- a/lib/Target/X86/X86Subtarget.h
+++ b/lib/Target/X86/X86Subtarget.h
@@ -215,6 +215,13 @@ public:
   /// indicating the number of scheduling cycles of backscheduling that
   /// should be attempted.
   unsigned getSpecialAddressLatency() const;
+
+  /// enablePostRAScheduler - X86 target is enabling post-alloc scheduling
+  /// at 'More' optimization level.
+  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
+    // FIXME: This causes llvm to miscompile itself on i386. :-(
+    return false/*OptLevel >= CodeGenOpt::Default*/;
+  }
 };
 
 } // End llvm namespace