diff options
author | Akira Hatanaka <ahatanaka@mips.com> | 2012-06-14 20:51:13 +0000 |
---|---|---|
committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-06-14 20:51:13 +0000 |
commit | 6b0cd9b9c65dc8c91827ddd926e050738ea590fd (patch) | |
tree | 431cd723e2878987d7a72061e438214b33cce4f6 | |
parent | 0180694b2f416e2247af1d284d701b19e1431a6c (diff) | |
download | external_llvm-6b0cd9b9c65dc8c91827ddd926e050738ea590fd.tar.gz external_llvm-6b0cd9b9c65dc8c91827ddd926e050738ea590fd.tar.bz2 external_llvm-6b0cd9b9c65dc8c91827ddd926e050738ea590fd.zip |
Make machine verifier check the first instruction of the last bundle instead of
the last instruction of a basic block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158468 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/CodeGen/MachineVerifier.cpp | 16 | ||||
-rw-r--r-- | test/CodeGen/Mips/machineverifier.ll | 21 |
2 files changed, 29 insertions, 8 deletions
diff --git a/lib/CodeGen/MachineVerifier.cpp b/lib/CodeGen/MachineVerifier.cpp index 7c64fc65e6..f6858543b3 100644 --- a/lib/CodeGen/MachineVerifier.cpp +++ b/lib/CodeGen/MachineVerifier.cpp @@ -476,8 +476,8 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) { report("MBB exits via unconditional fall-through but its successor " "differs from its CFG successor!", MBB); } - if (!MBB->empty() && MBB->back().isBarrier() && - !TII->isPredicated(&MBB->back())) { + if (!MBB->empty() && getBundleStart(&MBB->back())->isBarrier() && + !TII->isPredicated(getBundleStart(&MBB->back()))) { report("MBB exits via unconditional fall-through but ends with a " "barrier instruction!", MBB); } @@ -497,10 +497,10 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) { if (MBB->empty()) { report("MBB exits via unconditional branch but doesn't contain " "any instructions!", MBB); - } else if (!MBB->back().isBarrier()) { + } else if (!getBundleStart(&MBB->back())->isBarrier()) { report("MBB exits via unconditional branch but doesn't end with a " "barrier instruction!", MBB); - } else if (!MBB->back().isTerminator()) { + } else if (!getBundleStart(&MBB->back())->isTerminator()) { report("MBB exits via unconditional branch but the branch isn't a " "terminator instruction!", MBB); } @@ -520,10 +520,10 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) { if (MBB->empty()) { report("MBB exits via conditional branch/fall-through but doesn't " "contain any instructions!", MBB); - } else if (MBB->back().isBarrier()) { + } else if (getBundleStart(&MBB->back())->isBarrier()) { report("MBB exits via conditional branch/fall-through but ends with a " "barrier instruction!", MBB); - } else if (!MBB->back().isTerminator()) { + } else if (!getBundleStart(&MBB->back())->isTerminator()) { report("MBB exits via conditional branch/fall-through but the branch " "isn't a terminator instruction!", MBB); } @@ -540,10 +540,10 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) { if (MBB->empty()) { report("MBB exits via conditional branch/branch but doesn't " "contain any instructions!", MBB); - } else if (!MBB->back().isBarrier()) { + } else if (!getBundleStart(&MBB->back())->isBarrier()) { report("MBB exits via conditional branch/branch but doesn't end with a " "barrier instruction!", MBB); - } else if (!MBB->back().isTerminator()) { + } else if (!getBundleStart(&MBB->back())->isTerminator()) { report("MBB exits via conditional branch/branch but the branch " "isn't a terminator instruction!", MBB); } diff --git a/test/CodeGen/Mips/machineverifier.ll b/test/CodeGen/Mips/machineverifier.ll new file mode 100644 index 0000000000..c673fe557e --- /dev/null +++ b/test/CodeGen/Mips/machineverifier.ll @@ -0,0 +1,21 @@ +; RUN: llc < %s -march=mipsel -verify-machineinstrs +; Make sure machine verifier understands the last instruction of a basic block +; is not the terminator instruction after delay slot filler pass is run. + +@g = external global i32 + +define void @foo() nounwind { +entry: + %0 = load i32* @g, align 4 + %tobool = icmp eq i32 %0, 0 + br i1 %tobool, label %if.end, label %if.then + +if.then: ; preds = %entry + %add = add nsw i32 %0, 10 + store i32 %add, i32* @g, align 4 + br label %if.end + +if.end: ; preds = %entry, %if.then + ret void +} + |