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| author | Sean Callanan <scallanan@apple.com> | 2009-09-15 21:43:27 +0000 |
|---|---|---|
| committer | Sean Callanan <scallanan@apple.com> | 2009-09-15 21:43:27 +0000 |
| commit | 62c28e3f910e25e12957febbe3caac6566df0585 (patch) | |
| tree | 9c05cfd95a1b2084353fddd8139567ad72ddbfbc | |
| parent | 9b379dc52698a15ba474f570b5badf85b1903bfd (diff) | |
| download | external_llvm-62c28e3f910e25e12957febbe3caac6566df0585.tar.gz external_llvm-62c28e3f910e25e12957febbe3caac6566df0585.tar.bz2 external_llvm-62c28e3f910e25e12957febbe3caac6566df0585.zip | |
Updated comments per Eli's suggestion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81923 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86Instr64bit.td | 3 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td index 152cf2da15..dc98a2e309 100644 --- a/lib/Target/X86/X86Instr64bit.td +++ b/lib/Target/X86/X86Instr64bit.td @@ -458,7 +458,8 @@ def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem: [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))), (implicit EFLAGS)]>; -// Register-Register Addition +// Register-Register Addition - Equivalent to the normal rr form (ADD64rr), but +// differently encoded. def ADD64mrmrr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "add{l}\t{$src2, $dst|$dst, $src2}", []>; diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 923e2c2a4d..66bfdcdb34 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -2428,7 +2428,8 @@ def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))), (implicit EFLAGS)]>; -// Register-Register Addition +// Register-Register Addition - Equivalent to the normal rr forms (ADD8rr, +// ADD16rr, and ADD32rr), but differently encoded. def ADD8mrmrr: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), "add{b}\t{$src2, $dst|$dst, $src2}", []>; def ADD16mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2), |