diff options
| author | Johnny Chen <johnny.chen@apple.com> | 2010-01-25 21:56:35 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2010-01-25 21:56:35 +0000 |
| commit | 1b457cbee9b748a30b56c63c8a75a86cc13ea0f5 (patch) | |
| tree | 552a2e7aa14319968328bb8b5f544984db478ddc | |
| parent | 7fb6c5d677ec945129f1fe9a881a59bb819dc948 (diff) | |
| download | external_llvm-1b457cbee9b748a30b56c63c8a75a86cc13ea0f5.tar.gz external_llvm-1b457cbee9b748a30b56c63c8a75a86cc13ea0f5.tar.bz2 external_llvm-1b457cbee9b748a30b56c63c8a75a86cc13ea0f5.zip | |
Fixed the order of GPR RegisterClass regs to be: ..., R10, R11, R12, ...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94455 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index d393e8d7e3..e4b18088ad 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -123,7 +123,7 @@ def FPSCR : ARMReg<1, "fpscr">; // r10 == Stack Limit // def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, - R7, R8, R9, R10, R12, R11, + R7, R8, R9, R10, R11, R12, LR, SP, PC]> { let MethodProtos = [{ iterator allocation_order_begin(const MachineFunction &MF) const; |