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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-05-20 18:18:07 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-05-20 18:18:07 +0000 |
| commit | 1aeb13bd9cbc1be096af7d4f9da9d5fa566f606b (patch) | |
| tree | cc0817dd0e0538ab53423fa854d43465e350074a | |
| parent | f894199a14fff1399f6ee9d78c6a601d86649155 (diff) | |
| download | external_llvm-1aeb13bd9cbc1be096af7d4f9da9d5fa566f606b.tar.gz external_llvm-1aeb13bd9cbc1be096af7d4f9da9d5fa566f606b.tar.bz2 external_llvm-1aeb13bd9cbc1be096af7d4f9da9d5fa566f606b.zip | |
[mips] Add (setne $lhs, 0) instruction selection pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182307 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 2 | ||||
| -rw-r--r-- | test/CodeGen/Mips/setcc-se.ll | 10 |
2 files changed, 12 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index f7d21ce4d3..f37a93e887 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -1282,6 +1282,8 @@ multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, Instruction SLTuOp, Register ZEROReg> { def : MipsPat<(seteq RC:$lhs, 0), (SLTiuOp RC:$lhs, 1)>; + def : MipsPat<(setne RC:$lhs, 0), + (SLTuOp ZEROReg, RC:$lhs)>; def : MipsPat<(seteq RC:$lhs, RC:$rhs), (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; def : MipsPat<(setne RC:$lhs, RC:$rhs), diff --git a/test/CodeGen/Mips/setcc-se.ll b/test/CodeGen/Mips/setcc-se.ll index 6679536164..03af913860 100644 --- a/test/CodeGen/Mips/setcc-se.ll +++ b/test/CodeGen/Mips/setcc-se.ll @@ -9,3 +9,13 @@ entry: %conv = zext i1 %cmp to i32 ret i32 %conv } + +; CHECK: setne0: +; CHECK: sltu ${{[0-9]+}}, $zero, $4 + +define i32 @setne0(i32 %a) { +entry: + %cmp = icmp ne i32 %a, 0 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} |