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authorHeiko Schocher <hs@denx.de>2011-01-20 22:56:39 +0000
committerAlbert Aribaud <albert.aribaud@free.fr>2011-02-02 00:54:45 +0100
commitc9ac3ba129b242b5977b03c17ed8d2f0d000e085 (patch)
tree15731603c91122c1960fb365738e70e4f78b4b15 /arch
parent009b54079e65ddf004041ccaccef3b8647ce8a0b (diff)
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arm926ejs: timer: Replace bss variable by gdr
Reuse the gd->tbl value for timestamp and add gd->lastinc for lastinc bss values in the arm926ejs timers implementation. The usage of bss values in drivers before initialisation of bss is forbidden. In that special case some data in .rel.dyn gets corrupted. This patch is similiar to the patch Dirk Behme posted for the armv7/omap-common/timer.c and added suggestions from Reinhard Meyer. Tested on the arm926ejs mx27 based magnesium board Tested on the arm926ejs kirkwood based suen3 board Signed-off-by: Heiko Schocher <hs@denx.de> cc: Albert ARIBAUD <albert.aribaud@free.fr> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Stefano Babic <sbabic@denx.de> cc: Reinhard Meyer <u-boot@emk-elektronik.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/arm926ejs/kirkwood/timer.c6
-rw-r--r--arch/arm/cpu/arm926ejs/mb86r0x/timer.c6
-rw-r--r--arch/arm/cpu/arm926ejs/mx25/timer.c6
-rw-r--r--arch/arm/cpu/arm926ejs/mx27/timer.c6
-rw-r--r--arch/arm/cpu/arm926ejs/omap/timer.c6
-rw-r--r--arch/arm/cpu/arm926ejs/orion5x/timer.c6
-rw-r--r--arch/arm/cpu/arm926ejs/spear/timer.c6
-rw-r--r--arch/arm/cpu/arm926ejs/versatile/timer.c6
8 files changed, 32 insertions, 16 deletions
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/timer.c b/arch/arm/cpu/arm926ejs/kirkwood/timer.c
index 2ec6a9380..3e8032960 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/timer.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/timer.c
@@ -83,8 +83,10 @@ struct kwtmr_registers *kwtmr_regs = (struct kwtmr_registers *)KW_TIMER_BASE;
#define READ_TIMER (readl(CNTMR_VAL_REG(UBOOT_CNTR)) / \
(CONFIG_SYS_TCLK / 1000))
-static ulong timestamp;
-static ulong lastdec;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastdec gd->lastinc
void reset_timer_masked(void)
{
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
index 9175b71d1..6966b0d19 100644
--- a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
+++ b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
@@ -33,8 +33,10 @@
#define TIMER_LOAD_VAL 0xffffffff
#define TIMER_FREQ (CONFIG_MB86R0x_IOCLK / 256)
-static unsigned long long timestamp;
-static ulong lastdec;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastdec gd->lastinc
static inline unsigned long long tick_to_time(unsigned long long tick)
{
diff --git a/arch/arm/cpu/arm926ejs/mx25/timer.c b/arch/arm/cpu/arm926ejs/mx25/timer.c
index 11d41a8bf..14f0c2dc7 100644
--- a/arch/arm/cpu/arm926ejs/mx25/timer.c
+++ b/arch/arm/cpu/arm926ejs/mx25/timer.c
@@ -41,8 +41,10 @@
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-static ulong timestamp;
-static ulong lastinc;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastinc gd->lastinc
/*
* "time" is measured in 1 / CONFIG_SYS_HZ seconds,
diff --git a/arch/arm/cpu/arm926ejs/mx27/timer.c b/arch/arm/cpu/arm926ejs/mx27/timer.c
index 8f1d47bba..5c1cf014f 100644
--- a/arch/arm/cpu/arm926ejs/mx27/timer.c
+++ b/arch/arm/cpu/arm926ejs/mx27/timer.c
@@ -43,8 +43,10 @@
#define GPTCR_CLKSOURCE_32 (4 << 1) /* Clock source */
#define GPTCR_TEN 1 /* Timer enable */
-static ulong timestamp;
-static ulong lastinc;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastinc gd->lastinc
/*
* "time" is measured in 1 / CONFIG_SYS_HZ seconds,
diff --git a/arch/arm/cpu/arm926ejs/omap/timer.c b/arch/arm/cpu/arm926ejs/omap/timer.c
index 7d4b6e602..88a0ee677 100644
--- a/arch/arm/cpu/arm926ejs/omap/timer.c
+++ b/arch/arm/cpu/arm926ejs/omap/timer.c
@@ -42,8 +42,10 @@
/* macro to read the 32 bit timer */
#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+8))
-static ulong timestamp;
-static ulong lastdec;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastdec gd->lastinc
int timer_init (void)
{
diff --git a/arch/arm/cpu/arm926ejs/orion5x/timer.c b/arch/arm/cpu/arm926ejs/orion5x/timer.c
index 089ef47b3..bbab2269d 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/timer.c
+++ b/arch/arm/cpu/arm926ejs/orion5x/timer.c
@@ -90,8 +90,10 @@ static inline ulong read_timer(void)
/ (CONFIG_SYS_TCLK / 1000);
}
-static ulong timestamp;
-static ulong lastdec;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastdec gd->lastinc
void reset_timer_masked(void)
{
diff --git a/arch/arm/cpu/arm926ejs/spear/timer.c b/arch/arm/cpu/arm926ejs/spear/timer.c
index 06858b4a1..66cf4de81 100644
--- a/arch/arm/cpu/arm926ejs/spear/timer.c
+++ b/arch/arm/cpu/arm926ejs/spear/timer.c
@@ -36,8 +36,10 @@ static struct gpt_regs *const gpt_regs_p =
static struct misc_regs *const misc_regs_p =
(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-static ulong timestamp;
-static ulong lastdec;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastdec gd->lastinc
int timer_init(void)
{
diff --git a/arch/arm/cpu/arm926ejs/versatile/timer.c b/arch/arm/cpu/arm926ejs/versatile/timer.c
index 81d67490d..2e243b196 100644
--- a/arch/arm/cpu/arm926ejs/versatile/timer.c
+++ b/arch/arm/cpu/arm926ejs/versatile/timer.c
@@ -42,8 +42,10 @@
/* macro to read the 32 bit timer */
#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4))
-static ulong timestamp;
-static ulong lastdec;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastdec gd->lastinc
#define TIMER_ENABLE (1 << 7)
#define TIMER_MODE_MSK (1 << 6)