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| author | roy zang <tie-fei.zang@freescale.com> | 2006-12-04 17:54:21 +0800 |
|---|---|---|
| committer | Zang Tiefei <roy@bus.ap.freescale.net> | 2006-12-04 17:54:21 +0800 |
| commit | 4dbcd69e3e2776ea334590d5768e3692c5fae5c1 (patch) | |
| tree | f14a1b9562b8a71f77855e748716c373cf1749c6 | |
| parent | 4efe20c9579011d9987f62ed7d35ee8cdc1cf0e0 (diff) | |
| download | bootable_bootloader_goldelico_gta04-4dbcd69e3e2776ea334590d5768e3692c5fae5c1.tar.gz bootable_bootloader_goldelico_gta04-4dbcd69e3e2776ea334590d5768e3692c5fae5c1.tar.bz2 bootable_bootloader_goldelico_gta04-4dbcd69e3e2776ea334590d5768e3692c5fae5c1.zip | |
Introduce PLL_CFG[0:4] table for processor 7448/7447A/7455/7457. The original
multiplier table can not refect the real PLL clock behavior of these
processors. Please refer to the hardware specification for detailed
information of the corresponding processors.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
| -rw-r--r-- | cpu/74xx_7xx/speed.c | 18 |
1 files changed, 7 insertions, 11 deletions
diff --git a/cpu/74xx_7xx/speed.c b/cpu/74xx_7xx/speed.c index af4aca5c3..d8c40cea0 100644 --- a/cpu/74xx_7xx/speed.c +++ b/cpu/74xx_7xx/speed.c @@ -52,7 +52,8 @@ static const int hid1_multipliers_x_10[] = { 0 /* 1111 - off */ }; -static const int hid1_7447A_multipliers_x_10[] = { +/* PLL_CFG[0:4] table for cpu 7448/7447A/7455/7457 */ +static const int hid1_74xx_multipliers_x_10[] = { 115, /* 00000 - 11.5x */ 170, /* 00001 - 17x */ 75, /* 00010 - 7.5x */ @@ -66,7 +67,7 @@ static const int hid1_7447A_multipliers_x_10[] = { 65, /* 01010 - 6.5x */ 130, /* 01011 - 13x */ 85, /* 01100 - 8.5x */ - 240, /* 01101 - 13x */ + 240, /* 01101 - 24x */ 95, /* 01110 - 9.5x */ 90, /* 01111 - 9x */ 30, /* 10000 - 3x */ @@ -126,29 +127,24 @@ int get_clocks (void) { ulong clock = 0; -#ifdef CFG_CONFIG_BUS_CLK - gd->bus_clk = get_board_bus_clk (); /* bus clock is configurable */ -#else +#ifdef CFG_BUS_CLK gd->bus_clk = CFG_BUS_CLK; /* bus clock is a fixed frequency */ +#else + gd->bus_clk = get_board_bus_clk (); /* bus clock is configurable */ #endif /* calculate the clock frequency based upon the CPU type */ switch (get_cpu_type()) { case CPU_7447A: case CPU_7448: - clock = (gd->bus_clk / 10) * - hid1_7447A_multipliers_x_10[(get_hid1 () >> 12) & 0x1F]; - break; - case CPU_7455: case CPU_7457: /* - * It is assumed that the PLL_EXT line is zero. * Make sure division is done before multiplication to prevent 32-bit * arithmetic overflows which will cause a negative number */ clock = (gd->bus_clk / 10) * - hid1_multipliers_x_10[(get_hid1 () >> 13) & 0xF]; + hid1_74xx_multipliers_x_10[(get_hid1 () >> 12) & 0x1F]; break; case CPU_750GX: |