summaryrefslogtreecommitdiffstats
path: root/compiler/utils/arm64
Commit message (Collapse)AuthorAgeFilesLines
* Move mirror::ArtMethod to nativeMathieu Chartier2015-06-022-16/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Optimizing + quick tests are passing, devices boot. TODO: Test and fix bugs in mips64. Saves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS. Some of the savings are from removal of virtual methods and direct methods object arrays. Bug: 19264997 (cherry picked from commit e401d146407d61eeb99f8d6176b2ac13c4df1e33) Change-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d Fix some ArtMethod related bugs Added root visiting for runtime methods, not currently required since the GcRoots in these methods are null. Added missing GetInterfaceMethodIfProxy in GetMethodLine, fixes --trace run-tests 005, 044. Fixed optimizing compiler bug where we used a normal stack location instead of double on ARM64, this fixes the debuggable tests. TODO: Fix JDWP tests. Bug: 19264997 Change-Id: I7c55f69c61d1b45351fd0dc7185ffe5efad82bd3 ART: Fix casts for 64-bit pointers on 32-bit compiler. Bug: 19264997 Change-Id: Ief45cdd4bae5a43fc8bfdfa7cf744e2c57529457 Fix JDWP tests after ArtMethod change Fixes Throwable::GetStackDepth for exception event detection after internal stack trace representation change. Adds missing ArtMethod::GetInterfaceMethodIfProxy call in case of proxy method. Bug: 19264997 Change-Id: I363e293796848c3ec491c963813f62d868da44d2 Fix accidental IMT and root marking regression Was always using the conflict trampoline. Also included fix for regression in GC time caused by extra roots. Most of the regression was IMT. Fixed bug in DumpGcPerformanceInfo where we would get SIGABRT due to detached thread. EvaluateAndApplyChanges: From ~2500 -> ~1980 GC time: 8.2s -> 7.2s due to 1s less of MarkConcurrentRoots Bug: 19264997 Change-Id: I4333e80a8268c2ed1284f87f25b9f113d4f2c7e0 Fix bogus image test assert Previously we were comparing the size of the non moving space to size of the image file. Now we properly compare the size of the image space against the size of the image file. Bug: 19264997 Change-Id: I7359f1f73ae3df60c5147245935a24431c04808a [MIPS64] Fix art_quick_invoke_stub argument offsets. ArtMethod reference's size got bigger, so we need to move other args and leave enough space for ArtMethod* and 'this' pointer. This fixes mips64 boot. Bug: 19264997 Change-Id: I47198d5f39a4caab30b3b77479d5eedaad5006ab
* ART: Clean up arm64 kNumberOfXRegisters usage.Vladimir Marko2015-05-263-4/+1
| | | | | | | | | | | | | | | | | | | | | Avoid undefined behavior for arm64 stemming from 1u << 32 in loops with upper bound kNumberOfXRegisters. Create iterators for enumerating bits in an integer either from high to low or from low to high and use them for <arch>Context::FillCalleeSaves() on all architectures. Refactor runtime/utils.{h,cc} by moving all bit-fiddling functions to runtime/base/bit_utils.{h,cc} (together with the new bit iterators) and all time-related functions to runtime/base/time_utils.{h,cc}. Improve test coverage and fix some corner cases for the bit-fiddling functions. Bug: 13925192 (cherry picked from commit 80afd02024d20e60b197d3adfbb43cc303cf29e0) Change-Id: I905257a21de90b5860ebe1e39563758f721eab82
* Replace NULL with nullptrMathieu Chartier2015-04-221-3/+3
| | | | | | | Also fixed some lines that were too long, and a few other minor details. Change-Id: I6efba5fb6e03eb5d0a300fddb2a75bf8e2f175cb
* ARM64: Remove suspend register.Zheng Xu2015-04-142-68/+106
| | | | | | | | It also clean up build/remove frame used by JNI compiler and generates stp/ldp instead of str/ldr. Also x19 has been unblocked in both quick and optimizing compiler. Change-Id: Idbeac0942265f493266b2ef9b7a65bb4054f0e2d
* Implement CFI for JNI.David Srbecky2015-04-082-78/+44
| | | | | | CFI is necessary for stack unwinding in gdb, lldb, and libunwind. Change-Id: I37eb7973f99a6975034cf0e699e138c3a9aba10f
* ART: Enable more Clang warningsAndreas Gampe2015-04-061-0/+2
| | | | Change-Id: Ie6aba02f4223b1de02530e1515c63505f37e184c
* ARM64: Update to VIXL 1.9.Serban Constantinescu2015-03-311-2/+2
| | | | | | | Update VIXL's interface to VIXL 1.9. Change-Id: Iebae947539cbad65488b7195aaf01de284b71cbb Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
* Stack support for Optimizing compilerSebastien Hertz2015-03-032-3/+36
| | | | | | | | | | | Allows to read/write DEX registers from physical register or stack location when the method is compiled with the Optimizing compiler. Required fixing arm and arm64 JNI compiler by saving floating point registers. Bug: 18547544 Change-Id: I401579f251d1c0a130f6cf4a93a960cdcd7518f5
* Vixl: Update the VIXL interface to VIXL 1.7 and enable VIXL debug.Serban Constantinescu2014-11-281-6/+6
| | | | | | | | This patch updates the interface to VIXL 1.7 and enables the debug version of VIXL when ART is built in debug mode. Change-Id: I443fb941bec3cffefba7038f93bb972e6b7d8db5 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
* Fix the last users of TARGET_CPU_SMP.Elliott Hughes2014-11-191-2/+0
| | | | | | Everyone else assumes SMP. Change-Id: I7ff7faef46fbec6c67d6e446812d599e473cba39
* ART: More warningsAndreas Gampe2014-11-041-0/+5
| | | | | | | Enable -Wno-conversion-null, -Wredundant-decls and -Wshadow in general, and -Wunused-but-set-parameter for GCC builds. Change-Id: I81bbdd762213444673c65d85edae594a523836e5
* Remove -Wno-unused-parameter and -Wno-sign-promo from base cflags.Ian Rogers2014-11-031-1/+1
| | | | | | | | | | | Fix associated errors about unused paramenters and implict sign conversions. For sign conversion this was largely in the area of enums, so add ostream operators for the effected enums and fix tools/generate-operator-out.py. Tidy arena allocation code and arena allocated data types, rather than fixing new and delete operators. Remove dead code. Change-Id: I5b433e722d2f75baacfacae4d32aef4a828bfe1b
* ART: optimizing compiler: initial support for ARM64.Alexandre Rames2014-10-231-3/+4
| | | | | | | | | | The ARM64 port uses VIXL for code generation, to which it defers work like label binding and branch resolving, register type coherency checking, and immediate values handling. Change-Id: I0a44508c0c991f472a63e67b3469cdd878fe1a68 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com> Signed-off-by: Alexandre Rames <alexandre.rames@arm.com>
* Rename arm64 `Register` to `XRegister`.Alexandre Rames2014-10-175-302/+301
| | | | | | | This will avoid naming conflicts in the arm64 port of the optimizing compiler. Change-Id: Ie736ddd2ddbd2e299058256de28bad5d41c57d6f
* Rework arm64 register codes and fix Arm64ManagedRegister tests.Alexandre Rames2014-10-174-49/+24
| | | | Change-Id: I81ce3bc8a212c9c35be3a41b182ada87b32391ec
* stdint types all the way!Ian Rogers2014-10-091-1/+1
| | | | Change-Id: I4e4ef3a2002fc59ebd9097087f150eaf3f2a7e08
* ARM64: Update code after the VIXL 1.6 release.Alexandre Rames2014-10-093-10/+6
| | | | | | We now leave the assembler buffer management to VIXL. Change-Id: Ieefe83cf5cf5e1ab8c924b0e7dc03af6a55053ae
* Merge "Get heap poisoning working in 64-bit."Hiroshi Yamauchi2014-09-301-0/+4
|\
| * Get heap poisoning working in 64-bit.Hiroshi Yamauchi2014-09-291-0/+4
| | | | | | | | | | | | | | | | | | This adds the reference negate code in arm64 and x86_64 that's used by the jni compiler. Bug: 12687968 Bug: 8367515 Change-Id: I28a44bcead1ee613866645620b4eaf54fad6a3aa
* | ART: Fix some -Wpedantic errorsAndreas Gampe2014-09-291-1/+1
|/ | | | | | | | | | | | | | | | Remove extra semicolons. Dollar signs in C++ identifiers are an extension. Named variadic macros are an extension. Binary literals are a C++14 feature. Enum re-declarations are not allowed. Overflow. Change-Id: I7d16b2217b2ef2959ca69de84eaecc754517714a
* ARM64: Avoid the duplication of condition codes.Alexandre Rames2014-08-222-36/+16
|
* AArch64: Clean up CalleeSaveMethod frame and the use of temp registers.Zheng Xu2014-07-292-29/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | CalleeSaveMethod frame size changes : SaveAll : 368 -> 176 RefOnly : 176 -> 96 RefsAndArgs : 304 -> 224 JNI register spill size changes : 160 -> 88 In the transition assembly, use registers following the rules: 1. x0-x7 as temp/argument registers. 2. IP0, IP1 as scratch registers. 3. After correct type of callee-save-frame has been setup, all registers are scratch-able(probably except xSELF and xSUSPEND). 4. When restore callee-save-frame, IP0 and IP1 should be untouched. 5. From C to managed code, we assume all callee save register in AAPCS will be restored by managed code except x19(SUSPEND). In quick compiler: 1. Use IP0, IP1 as scratch register. 2. Use IP1 as hidden argument register(IP0 will be scratched by trampoline.) Change-Id: I05ed9d418b01b9e87218a7608536f57e7a286e4c
* ART: Fuse compare-with-0-and-branch in Arm64 utils-assemblerSerban Constantinescu2014-07-121-4/+2
| | | | | | | This patch squashes the use of cmp + b to cbz. Change-Id: I3d146a9921c471f08ba7304f1ca1b427d8e7dcf9 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
* ART: Use StackReference in Quick Stack FrameAndreas Gampe2014-05-291-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | The method reference at the bottom of a quick frame is a stack reference and not a native pointer. This is important for 64b architectures, where the notions do not coincide. Change key methods to have StackReference<mirror::ArtMethod>* parameter instead of mirror::ArtMethod**. Make changes to invoke stubs for 64b archs, change the frame setup for JNI code (both generic JNI and compilers), tie up loose ends. Tested on x86 and x86-64 with host tests. On x86-64, tests succeed with jni compiler activated. x86-64 QCG was not tested. Tested on ARM32 with device tests. Fix ARM64 not saving x19 (used for wSUSPEND) on upcalls. Tested on ARM64 in interpreter-only + generic-jni mode. Fix ARM64 JNI Compiler to work with the CL. Tested on ARM64 in interpreter-only + jni compiler. Change-Id: I77931a0cbadd04d163b3eb8d6f6a6f8740578f13
* Now we have a proper C++ library, use std::unique_ptr.Ian Rogers2014-05-191-2/+2
| | | | | | | Also remove the Android.libcxx.mk and other bits of stlport compatibility mechanics. Change-Id: Icdf7188ba3c79cdf5617672c1cfd0a68ae596a61
* Compatibility layer to transition from UniquePtr to std::unique_ptr.Ian Rogers2014-05-151-1/+1
| | | | | | | | | Use ART_WITH_STLPORT (enabled for the target) to cause the use of UniquePtr, for the host switch to std::unique_ptr. For now the type remains called UniquePtr. Make dalvik compile with clang on the host, move its build to C++11. Change-Id: I5ba8d2757904bc089ed62047ea03de3c0853fb12
* Add Handle/HandleScope and delete SirtRef.Mathieu Chartier2014-05-132-22/+22
| | | | | | | | | | | | | | | | Delete SirtRef and replaced it with Handle. Handles are value types which wrap around StackReference*. Renamed StackIndirectReferenceTable to HandleScope. Added a scoped handle wrapper which wraps around an Object** and restores it in its destructor. Renamed Handle::get -> Get. Bug: 8473721 Change-Id: Idbfebd4f35af629f0f43931b7c5184b334822c7a
* AArch64: Fix the usage of IP0, IP1 as temporary registersSerban Constantinescu2014-05-092-20/+36
| | | | | | | | | This patch fixes the usage of temporary registers by using VIXL's UseScratchRegisterScope. For the primitives used by the trampoline compiler we explicitly exclude IP0, IP1 from the temporary list. Change-Id: Icf9afbabd93214302891ddd536ce03a9c181463b Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
* AArch64: Fix the usage of Thread Register for arm64Serban Constantinescu2014-05-091-17/+23
| | | | | | | | | | | | | | | | This patch cleans-up the usage of x18 as TR for Arm64. As described in the Arm64 Procedure Call Standard, the recommended usage for x18 is to carry inter-procedural state (i.e. ART thread information). However, since x18 is a temporary register there is no guarantee that on calls to external functions x18 is preserved. Thus on JNI calls we need to save and restore x18 before coming back to managed runtime. For the JNI compiler trampoline we move x18 (temporary register - caller saved) to x19 (ETR, callee saved) before calling into native code, and restore it on the way back. Change-Id: If24091018d640027a497517a9238bf4a80d013aa Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
* ART: aarch64 jni compiler needs to extend small return typesAndreas Gampe2014-05-011-4/+18
| | | | | | | | | | | | | As aarch64 calling convention does not mandate extension on return values anymore and leaves the upper bits undefined, the jni compiler needs to sign- or zero-extend the returned values when necessary. As three architectures need extension now, refactor this fact into a flag into a virtual method. Add tests to JniTest that exercise the required extension. Change-Id: Idebb7c4dedebb852e58ade63e1c2b1eeced23104
* AArch64: Jni compiler fixesSerban Constantinescu2014-04-103-56/+108
| | | | | | | | | | | | | | | | | | | | | This patch fixes some of the issues with the ARM64 assembler and JNI compiler. The JNI compiler is not enabled by default, yet. To enable, change line 1884 in compiler/driver/compiler_driver.cc, removing kArm64 from the GenericJNI list. The compiler passes all tests in jni_compiler_test. Also change the common_compiler_test instruction-set-features logic. We allow tests when the build-time features are a subset of the runtime features. Dex2oat cross-compiling is now working. A 32b version of dex2oat should be able to compile correctly. Change-Id: I51d1c24f2c75d4397a11c54724a8b277ff3b3df8 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
* AArch64: Fix Managed Register unit testsSerban Constantinescu2014-04-074-14/+171
| | | | | | | | Fixes the XZR change introduced by one of the previous patches. It also adds extra testing for VIXL register integration. Change-Id: I4935f06726e25829613ef7bb6ac052d82056812c Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
* Do not output ARM64 assembler debug code.Andreas Gampe2014-04-031-11/+0
| | | | | | | This breaks the run tests, which are a simple diff against an expected output. Please do such changes in a local change. Change-Id: Ib961919600ba79eca1356278bc6c09ca17041c7c
* Calling convention support for cross 64/32 compilation.Ian Rogers2014-04-011-5/+7
| | | | | | Add REX support for x86-64 operands. Change-Id: I093ae26fb8c111d54b8c72166f054984564c04c6
* Allow mixing of thread offsets between 32 and 64bit architectures.Ian Rogers2014-04-013-74/+66
| | | | | | | Begin a more full implementation x86-64 REX prefixes. Doesn't implement 64bit thread offset support for the JNI compiler. Change-Id: If9af2f08a1833c21ddb4b4077f9b03add1a05147
* x86_64: JNI compilerDmitry Petrochenko2014-03-282-2/+2
| | | | | | | | | | | Passed all tests from jni_compiler_test and art/test on host with jni_copiler. Incoming argument spill is enabled, entry_spills refactored. Now each entry spill contains data type size (4 or 8) and offset which should be used for spill. Assembler REX support implemented in opcodes used in JNI compiler. Please note, JNI compiler is not enabled by default yet (see compiler_driver.cc:1875). Change-Id: I5fd19cca72122b197aec07c3708b1e80c324be44 Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
* Trampoline and assembly fixes for ARM64Andreas Gampe2014-03-242-0/+12
| | | | | | | | | | | Trampolines need a jump, not a call. Expose br in the ARM64 assembler to allow this. The resolution trampoline is called with the Quick ABI, and will continue to a Quick ABI function. Then the method pointer must be in x0. Change-Id: I4e383b59d6c40a659d324a7faef3fadf0c890178
* Some more ARM64 tests that are invalid at the momentAndreas Gampe2014-03-191-4/+6
| | | | Change-Id: I7e5a3c093bb0b0fd04ef588946f8b843993f6d4e
* Parts of ARM64 should not be enabled, yetAndreas Gampe2014-03-191-4/+5
| | | | | | | The managed register test exercises tests that are supposed to hold in the final product, but the infrastructure is not at that point yet. Change-Id: I32bee942a13819620d9f6b1c0d9a8a14c9951764
* AArch64: Add arm64 runtime support.Stuart Monteith2014-03-192-1/+2
| | | | | | | | | Adds support for arm64 to ART. Assembler stubs are sufficient for down calls into interpreter. JNI compiler and generics are not finished. Basic Generic JNI functionality. Change-Id: I4a07c79d1e037b9f5746673480e32cf456867b82
* Enable annotalysis on clang ART builds.Ian Rogers2014-03-061-4/+4
| | | | | | | | | | | Fix clang build errors aswell as restructure locking/mutex code for correct thread safety analysis support. Reorder make dependencies so that host builds build first as they should provide better compilation errors than target. Remove host's use of -fno-omit-frame-pointer as it has no value with correct use of CFI, which we should have. Change-Id: I72cea8da9a3757b1a0b3acb4081feccb7c6cef90
* AArch64: Add ARM64 AssemblerSerban Constantinescu2014-03-056-0/+1890
This patch adds the ARM64 Assembler and ManagedRegister backend. The implementation of the Arm64Assembler class is based on VIXL (a programmatic A64 Assembler - see external/vixl ). Change-Id: I842fd574637a953c19631eedf26f6c70d9ed7f9e Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2026-08-31 12:42:05 +0000