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* Fix a bug in the register allocator around pair allocation.Nicolas Geoffray2015-08-081-1/+4
| | | | | | | | | | | | | We may get hints that do not work with the current implementation of register pairs, which forces the allocation of (low + 1) for the high register. For example, if the hint is EBX, we will allocate ESP for the high register. bug:23043730 (cherry picked from commit f29758111e71a7d14f3e52d78773561a5d59961f) Change-Id: Ib395e36616017a87d3055218d72417f4e9ff6501
* MIPS: Initial version of optimizing compiler for MIPS64R6.Roland Levillain2015-06-261-0/+1
| | | | | | | | | | (cherry picked from commit 4dda3376b71209fae07f5c3c8ac3eb4b54207aa8) (amended for mnc-dev) Bug: 21555893 Change-Id: I874dc356eee6ab061a32f8f3df5f8ac3a4ab7dcf Signed-off-by: Alexey Frunze <Alexey.Frunze@imgtec.com> Signed-off-by: Douglas Leung <douglas.leung@imgtec.com>
* Move mirror::ArtMethod to nativeMathieu Chartier2015-06-021-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Optimizing + quick tests are passing, devices boot. TODO: Test and fix bugs in mips64. Saves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS. Some of the savings are from removal of virtual methods and direct methods object arrays. Bug: 19264997 (cherry picked from commit e401d146407d61eeb99f8d6176b2ac13c4df1e33) Change-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d Fix some ArtMethod related bugs Added root visiting for runtime methods, not currently required since the GcRoots in these methods are null. Added missing GetInterfaceMethodIfProxy in GetMethodLine, fixes --trace run-tests 005, 044. Fixed optimizing compiler bug where we used a normal stack location instead of double on ARM64, this fixes the debuggable tests. TODO: Fix JDWP tests. Bug: 19264997 Change-Id: I7c55f69c61d1b45351fd0dc7185ffe5efad82bd3 ART: Fix casts for 64-bit pointers on 32-bit compiler. Bug: 19264997 Change-Id: Ief45cdd4bae5a43fc8bfdfa7cf744e2c57529457 Fix JDWP tests after ArtMethod change Fixes Throwable::GetStackDepth for exception event detection after internal stack trace representation change. Adds missing ArtMethod::GetInterfaceMethodIfProxy call in case of proxy method. Bug: 19264997 Change-Id: I363e293796848c3ec491c963813f62d868da44d2 Fix accidental IMT and root marking regression Was always using the conflict trampoline. Also included fix for regression in GC time caused by extra roots. Most of the regression was IMT. Fixed bug in DumpGcPerformanceInfo where we would get SIGABRT due to detached thread. EvaluateAndApplyChanges: From ~2500 -> ~1980 GC time: 8.2s -> 7.2s due to 1s less of MarkConcurrentRoots Bug: 19264997 Change-Id: I4333e80a8268c2ed1284f87f25b9f113d4f2c7e0 Fix bogus image test assert Previously we were comparing the size of the non moving space to size of the image file. Now we properly compare the size of the image space against the size of the image file. Bug: 19264997 Change-Id: I7359f1f73ae3df60c5147245935a24431c04808a [MIPS64] Fix art_quick_invoke_stub argument offsets. ArtMethod reference's size got bigger, so we need to move other args and leave enough space for ArtMethod* and 'this' pointer. This fixes mips64 boot. Bug: 19264997 Change-Id: I47198d5f39a4caab30b3b77479d5eedaad5006ab
* Add a parent environment to HEnvironment.Nicolas Geoffray2015-05-111-3/+4
| | | | | | | This code has no functionality change. It adds a placeholder for chaining inlined frames. Change-Id: I5ec57335af76ee406052345b947aad98a6a4423a
* Find better split positions in the register allocator.Nicolas Geoffray2015-05-051-3/+38
| | | | | | | | | | | In a standard if/else control flow graph, this avoids doing a move in one branch if the other branch decided to move an interval. This also needs a new register hint kind, which is what was the location of the interval at the predecessor block. Change-Id: I18b78264587b4d693540fbb5e014d12df2add3e2
* Add synthesize uses at back edge.Nicolas Geoffray2015-04-291-14/+25
| | | | | | | | | This reduces the cost of linearizing the graph (hence removing the notion of back edge). Since linear scan allocates/spills registers based on next use, adding a use at a back edge ensures we do count for loop uses. Change-Id: Idaa882cb120edbdd08ca6bff142d326a8245bd14
* Dissociate uses with environment uses.Nicolas Geoffray2015-04-271-27/+28
| | | | | | | They are most of the times in the way when iterating. They also complicate the logic of (future) back edge uses. Change-Id: I152595d9913073fe901b267ca623fa0fe7432484
* Linear scan: split at better positions.Nicolas Geoffray2015-04-231-2/+27
| | | | | | | - Split at block entry to piggy back on control flow resolution. - Split at the loop header, if the split position is within a loop. Change-Id: I718299a58c02ee02a1b22bda589607c69a35f0e8
* Merge "Linear scan: Use FirstUse instead of FirstRegisterUse."Nicolas Geoffray2015-04-211-7/+13
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| * Linear scan: Use FirstUse instead of FirstRegisterUse.Nicolas Geoffray2015-04-211-7/+13
| | | | | | | | | | | | This is in preparation for introducing synthesized used at back edges. Change-Id: Ie28d6725d2dde982cf2137f2110daabcbab9f789
* | ART: Improve range search caching in LiveIntervalDavid Brazdil2015-04-171-5/+7
|/ | | | | | | | | | | Register allocator spends too long in LiveInterval queries. This patch builds on previously introduced caching of range search results to further speed up LiveInterval's Covers and FindIntersectionWith. Only calls which are guaranteed to query the current->GetStart() position are cached. Other calls are replaced with CoversSlow which searches through the entire list of ranges. Change-Id: I84d92b526e174caa70d6477497a06afd85016c4a
* ART: Replace expensive calls to Covers in reg allocDavid Brazdil2015-04-161-24/+3
| | | | | | | | | LiveInterval::Covers is implemented as a linear-time search over liveness ranges and can therefore be rather expensive and should be avoided unless necessary. This patch replaces calls to Covers when searching for a sibling with the cheaper IsDefinedAt call. Change-Id: I93fc73529c15a518335f4cbdc3a0def52d9501e5
* Split safepoint positions to avoid calling Covers.Nicolas Geoffray2015-04-161-7/+4
| | | | | | | This is also in preparation for caller/callee save based register allocation. Change-Id: I63954bdae5ea7870568fd93b4d11e1c9dcd6de6f
* Merge "Type MoveOperands."Nicolas Geoffray2015-04-151-3/+3
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| * Type MoveOperands.Nicolas Geoffray2015-04-151-3/+3
| | | | | | | | | | | | | | | | | | The ParallelMoveResolver implementation needs to know if a move is for 64bits or not, to handle swaps correctly. Bug found, and test case courtesy of Serguei I. Katkov. Change-Id: I9a0917a1cfed398c07e57ad6251aea8c9b0b8506
* | Move the linear order to the HGraph.Nicolas Geoffray2015-04-151-5/+5
|/ | | | | | | | | Bug found by Zheng Xu: SsaLivenessAnalysis being a stack allocated object, we should not refer to it in later phases of the compiler. Specifically, the code generator was using the linear order, which was stored in the liveness analysis object. Change-Id: I574641f522b7b86fc43f3914166108efc72edb3b
* Refactor safepoints in register allocator.Nicolas Geoffray2015-04-151-21/+30
| | | | | | | This is in preparation for adding logic around callee/caller saved in the register allocator. Change-Id: I4204169f0a6a01074880538833144be7b0810882
* Fix lint error.Nicolas Geoffray2015-03-311-1/+1
| | | | Change-Id: I39dda83acd755b2c95453b3b0f7774bc9d18546e
* Fix locations at environment uses.Nicolas Geoffray2015-03-311-18/+36
| | | | | | | | | We were too agressive in not recording environment uses when the instruction was not of type object. We have to record the use to the use list of an interval, but it should not affect the live ranges of that interval. Change-Id: Id16fb7cc06f14083766d408a345837793583b6ea
* Merge "Implement a proper solution for temps."Nicolas Geoffray2015-03-301-13/+6
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| * Implement a proper solution for temps.Nicolas Geoffray2015-03-271-13/+6
| | | | | | | | | | | | | | | | We used to play some trickery when updating locations of temps. This change creates a proper use of the temp, and use it for updating its location. Change-Id: I53e9447b87a55137a3a79841db21ad3864854825
* | Fix user-build on fugu.Nicolas Geoffray2015-03-301-39/+25
|/ | | | | | | | | Calling Delete on an array shifts the elements, so when iterating over inactives and removing entries we need to decrement for the found interval, but also its potential other half. The code used to not decrement for the other half Change-Id: Idcb1533643c11a37ed4f459fe88aaef208a4bfd6
* Revert "Revert "[optimizing] Enable x86 long support.""Nicolas Geoffray2015-03-111-47/+79
| | | | | | This reverts commit 154552e666347d41d95d7619c6ee56249ff4feca. Change-Id: Idc726551c249a888b7ff5fde8508ae50e81b2e13
* Merge "Revert "[optimizing] Enable x86 long support.""Nicolas Geoffray2015-03-061-68/+42
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| * Revert "[optimizing] Enable x86 long support."Nicolas Geoffray2015-03-061-68/+42
| | | | | | | | | | | | | | | | Few libcore failures. This reverts commit b4ba354cf8d22b261205494875cc014f18587b50. Change-Id: I4a28d853e730dff9b69aec9555505803cf2fcd63
* | Merge "[optimizing] Enable x86 long support."Nicolas Geoffray2015-03-061-42/+68
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| * [optimizing] Enable x86 long support.Nicolas Geoffray2015-03-061-42/+68
| | | | | | | | Change-Id: I9006972a65a1f191c45691104a960366747f9d16
* | ART: Fix test breakageDavid Brazdil2015-03-051-4/+4
| | | | | | | | | | | | | | | | Recent commit changed the direction of iteration over safepoints in the register allocator but contained a bug that skipped some of them at the boundaries of interval siblings. This patch fixes the bug. Change-Id: Ia7d4892536b5198e01c9bc3034f448227794ff72
* | ART: Optimize iteration of safepointsDavid Brazdil2015-03-051-6/+15
|/ | | | | | | | | The LiveInterval::Covers method is optimized for multiple calls with non-decreasing positions. This patch reverts the order of iteration over safepoints in RegisterAllocator::ConnectSiblings to capitalize on this effect. Change-Id: Ieb70eb9d5c0a06ee79379aab6c87cb3290c15bf7
* Each primitive kind now spills to different locations.Nicolas Geoffray2015-02-231-22/+79
| | | | | | | | Having different slots depending on the types greatly simplifies the parallel move resolver. It also avoids doing FPU <-> Core register swaps, and force backends to implement such a swap. Change-Id: Ide9f0452e7ccf9efb8adddbcc246d44b937b253c
* Optimize leaf methods.Nicolas Geoffray2015-02-061-2/+7
| | | | | | Avoid suspend checks and stack changes when not needed. Change-Id: I0fdb31e8c631e99091b818874a558c9aa04b1628
* Finally implement Location::kNoOutputOverlap.Nicolas Geoffray2015-02-041-1/+53
| | | | | | | | | | The [i, i + 1) interval scheme we chose for representing lifetime positions is not optimal for doing this optimization. It however doesn't prevent recognizing a non-split interval during the TryAllocateFreeReg phase, and try to re-use its inputs' registers. Change-Id: I80a2823b0048d3310becfc5f5fb7b1230dfd8201
* Use a different block order when not compiling baseline.Nicolas Geoffray2015-02-031-3/+5
| | | | | | | | Use the linearized order instead, as it puts blocks logically next to each other in a better way. Also, it does not contain dead blocks. Change-Id: Ie65b56041a093c8155e6c1e06351cb36a4053505
* [optimizing compiler] Support x86 hard float ABIMark Mendell2015-01-281-6/+2
| | | | | | | | Add support for the new ABI passing FP parameters in XMM0-XMM3. This allows us to optimize for x86 methods that don't use 'long'. Change-Id: Ic79a24767173451e7d7095ccc2a00b307593a868 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Enable core callee-save on x64.Nicolas Geoffray2015-01-211-10/+20
| | | | | | Will work on other architectures and FP support in other CLs. Change-Id: I8cef0343eedc7202d206f5217fdf0349035f0e4d
* Revert "Revert "Fully support pairs in the register allocator.""Nicolas Geoffray2015-01-211-29/+117
| | | | | | This reverts commit c399fdc442db82dfda66e6c25518872ab0f1d24f. Change-Id: I19f8215c4b98f2f0827e04bf7806c3ca439794e5
* Revert "Fully support pairs in the register allocator."Nicolas Geoffray2015-01-211-113/+29
| | | | | | | | Libcore tests fail. This reverts commit 41aedbb684ccef76ff8373f39aba606ce4cb3194. Change-Id: I2572f120d4bbaeb7a4d4cbfd47ab00c9ea39ac6c
* Fully support pairs in the register allocator.Nicolas Geoffray2015-01-211-29/+113
| | | | | | Enabled on ARM for longs and doubles. Change-Id: Id8792d08bd7ca9fb049c5db8a40ae694bafc2d8b
* Do not use register pair in a parallel move.Nicolas Geoffray2015-01-161-5/+5
| | | | | | | The ParallelMoveResolver does not work with pairs. Instead, decompose the pair into two individual moves. Change-Id: Ie9d3f0b078cef8dc20640c98b20bb20cc4971a7f
* Merge "Fix a bug in the register allocator."Nicolas Geoffray2015-01-161-2/+9
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| * Fix a bug in the register allocator.Nicolas Geoffray2015-01-161-2/+9
| | | | | | | | | | | | | | | | | | | | When allocating a register blocked by existing intervals, we need to split inactive intervals at the end of their lifetime hole, and not at the next intersection. Otherwise, the allocation for following intervals will not see that a register is being used by the split interval. Change-Id: I40cc79dde541c07392a7cf4c6f0b291dd1ce1819
* | ART: Optimizing compiler intrinsicsAndreas Gampe2015-01-151-4/+11
| | | | | | | | | | | | | | | | | | Add intrinsics infrastructure to the optimizing compiler. Add almost all intrinsics supported by Quick to the x86-64 backend. Further intrinsics require more assembler support. Change-Id: I48de9b44c82886bb298d16e74e12a9506b8e8807
* | [optimizing compiler] Compute live spill sizeMark Mendell2015-01-151-10/+14
|/ | | | | | | | | | | | | | | | | The current stack frame calculation assumes that each live register to be saved/restored has the word size of the machine. This fails for X86, where a double in an XMM register takes up 8 bytes. Change the calculation to keep track of the number of core registers and number of fp registers to handle this distinction. This is slightly pessimal, as the registers may not be active at the same time, but the only way to handle this would be to allocate both classes of registers simultaneously, or remember all the active intervals, matching them up and compute the size of each safepoint interval. Change-Id: If7860aa319b625c214775347728cdf49a56946eb Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Implement double and float support for arm in register allocator.Nicolas Geoffray2015-01-081-36/+163
| | | | | | | | | | | | The basic approach is: - An instruction that needs two registers gets two intervals. - When allocating the low part, we also allocate the high part. - When splitting a low (or high) interval, we also split the high (or low) equivalent. - Allocation follows the (S/D register) requirement that low registers are always even and the high equivalent is low + 1. Change-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797
* Opt compiler: Add arm64 support for register allocation.Alexandre Rames2014-12-101-4/+6
| | | Change-Id: Idc6e84eee66170de4a9c0a5844c3da038c083aa7
* Fix insertion of parallel move when connecting siblings.Nicolas Geoffray2014-12-011-4/+31
| | | | | | | | | | | | Also add a check that ensures parallel moves have been inserted correctly. This fixes tests: org.apache.harmony.tests.java.util.BitSetTest#test_nextSetBitI org.apache.harmony.tests.java.util.BitSetTest#test_31036_set On host/x64. Change-Id: I59d29aca393b5344bac933e2813ab409fea9d9b5
* Merge "Fix a bug in the linear scan register allocator."Nicolas Geoffray2014-11-281-10/+26
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| * Fix a bug in the linear scan register allocator.Nicolas Geoffray2014-11-261-10/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Triggered by: org.apache.harmony.tests.java.util.jar.JarFileTest#testGetJarEntry. By miscompling: okhttp.CacheControl#parse. A move occuring just before the first instruction of a block should not be handled by ConnectSplitSiblings, but by ConnectSiblings instead. Change-Id: I8ad409734809e6787bb7321563e1331e7a6906c0
* | Merge "Fix bogus assumption for live registers at safe point."Nicolas Geoffray2014-11-281-18/+17
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| * | Fix bogus assumption for live registers at safe point.Nicolas Geoffray2014-11-261-18/+17
| |/ | | | | | | | | | | | | | | | | | | We did not take into account inactive intervals going into active when computing live registers at a slow path safe point. So we must ensure the safepoint interval is always handled after all intervals starting at the same position have been handled. Change-Id: I05ea2161016a90b0ee3ba0b18cd54a8e46860f1e
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