Merge "Opt Compiler: ARM64 goodness"

2 files changed, 6 insertions, 7 deletions

diff --git a/runtime/arch/arm64/instruction_set_features_arm64.h b/runtime/arch/arm64/instruction_set_features_arm64.h
index 3b3e2c95fe..e59ff58954 100644
--- a/runtime/arch/arm64/instruction_set_features_arm64.h
+++ b/runtime/arch/arm64/instruction_set_features_arm64.h
@@ -66,13 +66,12 @@ class Arm64InstructionSetFeatures FINAL : public InstructionSetFeatures {
       return fix_cortex_a53_843419_;
   }
 
-  // TODO: Tune this on a per CPU basis. For now, we pessimistically assume
-  // that all ARM64 CPUs prefer explicit memory barriers over acquire-release.
-  //
-  // NOTE: This should not be the case! However we want to exercise the
-  // explicit memory barriers code paths in the Optimizing Compiler.
+  // NOTE: This flag can be tunned on a CPU basis. In general all ARMv8 CPUs
+  // should prefer the Acquire-Release semantics over the explicit DMBs when
+  // handling load/store-volatile. For a specific use case see the ARM64
+  // Optimizing backend.
   bool PreferAcquireRelease() const {
-    return false;
+    return true;
   }
 
   virtual ~Arm64InstructionSetFeatures() {}
diff --git a/runtime/arch/arm64/instruction_set_features_arm64_test.cc b/runtime/arch/arm64/instruction_set_features_arm64_test.cc
index 753107baa8..599f24ed30 100644
--- a/runtime/arch/arm64/instruction_set_features_arm64_test.cc
+++ b/runtime/arch/arm64/instruction_set_features_arm64_test.cc
@@ -31,7 +31,7 @@ TEST(Arm64InstructionSetFeaturesTest, Arm64Features) {
   EXPECT_STREQ("smp,a53", arm64_features->GetFeatureString().c_str());
   EXPECT_EQ(arm64_features->AsBitmap(), 3U);
   // See the comments in instruction_set_features_arm64.h.
-  EXPECT_FALSE(arm64_features->AsArm64InstructionSetFeatures()->PreferAcquireRelease());
+  EXPECT_TRUE(arm64_features->AsArm64InstructionSetFeatures()->PreferAcquireRelease());
 }
 
 }  // namespace art