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| author | Zheng Xu <zheng.xu@arm.com> | 2015-02-15 18:39:46 +0800 |
|---|---|---|
| committer | Zheng Xu <zheng.xu@arm.com> | 2015-02-16 19:20:16 +0800 |
| commit | a3ec39425e09f92421775d1485660eb633f97aec (patch) | |
| tree | 6b260d01cf8aa3bb0eaa4e45792302902f54952c /compiler | |
| parent | e5f5953e744060fde3b4489cea4d934d529e3e32 (diff) | |
| download | art-a3ec39425e09f92421775d1485660eb633f97aec.tar.gz art-a3ec39425e09f92421775d1485660eb633f97aec.tar.bz2 art-a3ec39425e09f92421775d1485660eb633f97aec.zip | |
Opt compiler: ARM64: Fix blocking fp registers.
VIXL reserved float point registers has not been blocked correctly.
Change-Id: Ie7131d86bbaff48c431e3e26abd2fa26389ac687
Diffstat (limited to 'compiler')
| -rw-r--r-- | compiler/optimizing/code_generator_arm64.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/compiler/optimizing/code_generator_arm64.cc b/compiler/optimizing/code_generator_arm64.cc index 46f1a9b51d..ec716a414e 100644 --- a/compiler/optimizing/code_generator_arm64.cc +++ b/compiler/optimizing/code_generator_arm64.cc @@ -577,7 +577,7 @@ void CodeGeneratorARM64::SetupBlockedRegisters(bool is_baseline) const { } CPURegList reserved_fp_registers = vixl_reserved_fp_registers; - while (!reserved_core_registers.IsEmpty()) { + while (!reserved_fp_registers.IsEmpty()) { blocked_fpu_registers_[reserved_fp_registers.PopLowestIndex().code()] = true; } |