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| author | David Srbecky <dsrbecky@google.com> | 2015-04-20 16:43:52 +0100 |
|---|---|---|
| committer | Andreas Gampe <agampe@google.com> | 2015-04-22 14:19:16 -0700 |
| commit | 8a813f72d21dea87b9e94b686fb35868ad4a88c4 (patch) | |
| tree | b442306bde33fe6fb6afd7c8ee65a8ec95aeaf4a /compiler | |
| parent | be52c68dca2f146a571ffa65624acf2e6c7adeb2 (diff) | |
| download | art-8a813f72d21dea87b9e94b686fb35868ad4a88c4.tar.gz art-8a813f72d21dea87b9e94b686fb35868ad4a88c4.tar.bz2 art-8a813f72d21dea87b9e94b686fb35868ad4a88c4.zip | |
Do not mention x86 floating point numbers in CFI.
We have explicitly declared them as undefined, but libunwind does
not seem to support them at all. Omit the initialization to make
libunwind happy. Reasonable debugger should still default to
undefined since they are not callee save registers.
Bug: 20491296
Change-Id: Ibaa9595b977508e518bfe3f88b240e8959b1198f
Diffstat (limited to 'compiler')
| -rw-r--r-- | compiler/dwarf/register.h | 1 | ||||
| -rw-r--r-- | compiler/elf_writer_debug.cc | 8 |
2 files changed, 7 insertions, 2 deletions
diff --git a/compiler/dwarf/register.h b/compiler/dwarf/register.h index fa666dffa9..70452377dd 100644 --- a/compiler/dwarf/register.h +++ b/compiler/dwarf/register.h @@ -33,6 +33,7 @@ class Reg { // There are ways around this in DWARF but they are complex. // It would be much simpler to always spill whole D registers. // Arm64 mapping is correct since we already do this there. + // libunwind might struggle with the new mapping as well. static Reg ArmCore(int num) { return Reg(num); } static Reg ArmFp(int num) { return Reg(64 + num); } // S0–S31. diff --git a/compiler/elf_writer_debug.cc b/compiler/elf_writer_debug.cc index cf0adae525..28e6999472 100644 --- a/compiler/elf_writer_debug.cc +++ b/compiler/elf_writer_debug.cc @@ -99,6 +99,8 @@ static void WriteEhFrameCIE(InstructionSet isa, return; } case kX86: { + // FIXME: Add fp registers once libunwind adds support for them. Bug: 20491296 + constexpr bool generate_opcodes_for_x86_fp = false; DebugFrameOpCodeWriter<> opcodes; opcodes.DefCFA(Reg::X86Core(4), 4); // R4(ESP). opcodes.Offset(Reg::X86Core(8), -4); // R8(EIP). @@ -113,8 +115,10 @@ static void WriteEhFrameCIE(InstructionSet isa, } } // fp registers. - for (int reg = 0; reg < 8; reg++) { - opcodes.Undefined(Reg::X86Fp(reg)); + if (generate_opcodes_for_x86_fp) { + for (int reg = 0; reg < 8; reg++) { + opcodes.Undefined(Reg::X86Fp(reg)); + } } auto return_reg = Reg::X86Core(8); // R8(EIP). WriteEhFrameCIE(is64bit, addr_type, return_reg, opcodes, eh_frame); |