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authorArtem Serov <artem.serov@linaro.org>2017-10-05 16:48:30 +0100
committerArtem Serov <artem.serov@linaro.org>2017-10-12 18:04:48 +0100
commit6e9b137f0439b3ceedb8114bd93fa9fb746e42fa (patch)
tree1fc138f4f0727fe4e78141fb2979c665d1fe157b /compiler/optimizing/loop_optimization.cc
parent4c3682649ebcaef4ab237f523f8e39ebd65e4f8d (diff)
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ARM: Support SIMD reduction for 32-bit backend.
Support SIMD reduction (add, min, max) and SAD (for int->int only) idioms for arm (32-bit) backend. Test: test-art-target, test-art-host Test: 661-checker-simd-reduc, 660-checker-simd-sad-int Change-Id: Ic6121f5d781a9bcedc33041b6c4ecafad9b0420a
Diffstat (limited to 'compiler/optimizing/loop_optimization.cc')
-rw-r--r--compiler/optimizing/loop_optimization.cc6
1 files changed, 4 insertions, 2 deletions
diff --git a/compiler/optimizing/loop_optimization.cc b/compiler/optimizing/loop_optimization.cc
index d87861bde0..645915e2f8 100644
--- a/compiler/optimizing/loop_optimization.cc
+++ b/compiler/optimizing/loop_optimization.cc
@@ -1359,7 +1359,7 @@ bool HLoopOptimization::TrySetVectorType(DataType::Type type, uint64_t* restrict
*restrictions |= kNoDiv | kNoStringCharAt | kNoReduction;
return TrySetVectorLength(4);
case DataType::Type::kInt32:
- *restrictions |= kNoDiv | kNoReduction;
+ *restrictions |= kNoDiv | kNoWideSAD;
return TrySetVectorLength(2);
default:
break;
@@ -1968,7 +1968,9 @@ bool HLoopOptimization::VectorizeSADIdiom(LoopNode* node,
return false;
}
// Try same/narrower type and deal with vector restrictions.
- if (!TrySetVectorType(sub_type, &restrictions) || HasVectorRestrictions(restrictions, kNoSAD)) {
+ if (!TrySetVectorType(sub_type, &restrictions) ||
+ HasVectorRestrictions(restrictions, kNoSAD) ||
+ (reduction_type != sub_type && HasVectorRestrictions(restrictions, kNoWideSAD))) {
return false;
}
// Accept SAD idiom for vectorizable operands. Vectorized code uses the shorthand