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| author | Roland Levillain <rpl@google.com> | 2017-07-14 14:34:22 +0100 |
|---|---|---|
| committer | Roland Levillain <rpl@google.com> | 2017-07-14 17:25:39 +0100 |
| commit | 9983e302384c12a975c8d2d5ae239f79fd8e1996 (patch) | |
| tree | 4e4d269fe1a3d4f0f1b93cd972adab9f17aab8e0 /compiler/optimizing/instruction_simplifier_shared.cc | |
| parent | bac2bd1c2fbdd94f4d4dfe83d8451f655e875e36 (diff) | |
| download | art-9983e302384c12a975c8d2d5ae239f79fd8e1996.tar.gz art-9983e302384c12a975c8d2d5ae239f79fd8e1996.tar.bz2 art-9983e302384c12a975c8d2d5ae239f79fd8e1996.zip | |
Remove the old ARM code generator from ART's Optimizing compiler.
The AArch32 VIXL-based code generator has been the default
ARM code generator in ART for some time now. The old ARM
code generator does not compile anymore; retiring it.
Test: test.py
Bug: 63316036
Change-Id: Iab8fbc4ac73eac2c1a809cd7b22fec6b619755db
Diffstat (limited to 'compiler/optimizing/instruction_simplifier_shared.cc')
| -rw-r--r-- | compiler/optimizing/instruction_simplifier_shared.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/compiler/optimizing/instruction_simplifier_shared.cc b/compiler/optimizing/instruction_simplifier_shared.cc index e5a8499ff4..d1bc4dadeb 100644 --- a/compiler/optimizing/instruction_simplifier_shared.cc +++ b/compiler/optimizing/instruction_simplifier_shared.cc @@ -274,8 +274,8 @@ bool TryExtractArrayAccessAddress(HInstruction* access, // `HArm64Load` and `HArm64Store`,`HArmLoad` and `HArmStore`). We defer these changes // because these new instructions would not bring any advantages yet. // Also see the comments in - // `InstructionCodeGeneratorARM::VisitArrayGet()` - // `InstructionCodeGeneratorARM::VisitArraySet()` + // `InstructionCodeGeneratorARMVIXL::VisitArrayGet()` + // `InstructionCodeGeneratorARMVIXL::VisitArraySet()` // `InstructionCodeGeneratorARM64::VisitArrayGet()` // `InstructionCodeGeneratorARM64::VisitArraySet()`. return true; |