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| author | Goran Jakovljevic <goran.jakovljevic@mips.com> | 2017-11-08 10:16:37 +0100 |
|---|---|---|
| committer | Goran Jakovljevic <goran.jakovljevic@mips.com> | 2017-11-08 10:27:56 +0100 |
| commit | 7a0222e78ca39dc8f8e084b0c84f71a10852d24a (patch) | |
| tree | e52cd11e0080787d9476d74f88571a9497d25b56 /compiler/optimizing/code_generator_vector_mips.cc | |
| parent | db9f630e2396f1dd0f640b10253230cf966cc526 (diff) | |
| download | art-7a0222e78ca39dc8f8e084b0c84f71a10852d24a.tar.gz art-7a0222e78ca39dc8f8e084b0c84f71a10852d24a.tar.bz2 art-7a0222e78ca39dc8f8e084b0c84f71a10852d24a.zip | |
MIPS32: Don't leave vector registers in an unpredictable state
Don't use regular FPU instructions in the Vectorizer because some
of those (such as mtc1 and mthc1) may leave remaining elements in
an unpredictable state.
Test: ./testrunner --optimizing --target --32 in QEMU (MIPS32R6)
Change-Id: I9b082bfd83360374b2f4831ef5f5bd35b00272a5
Diffstat (limited to 'compiler/optimizing/code_generator_vector_mips.cc')
| -rw-r--r-- | compiler/optimizing/code_generator_vector_mips.cc | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/compiler/optimizing/code_generator_vector_mips.cc b/compiler/optimizing/code_generator_vector_mips.cc index 7a8c0ad025..384b642145 100644 --- a/compiler/optimizing/code_generator_vector_mips.cc +++ b/compiler/optimizing/code_generator_vector_mips.cc @@ -68,8 +68,12 @@ void InstructionCodeGeneratorMIPS::VisitVecReplicateScalar(HVecReplicateScalar* break; case DataType::Type::kInt64: DCHECK_EQ(2u, instruction->GetVectorLength()); - __ Mtc1(locations->InAt(0).AsRegisterPairLow<Register>(), FTMP); - __ MoveToFpuHigh(locations->InAt(0).AsRegisterPairHigh<Register>(), FTMP); + __ InsertW(static_cast<VectorRegister>(FTMP), + locations->InAt(0).AsRegisterPairLow<Register>(), + 0); + __ InsertW(static_cast<VectorRegister>(FTMP), + locations->InAt(0).AsRegisterPairHigh<Register>(), + 1); __ ReplicateFPToVectorRegister(dst, FTMP, /* is_double */ true); break; case DataType::Type::kFloat32: @@ -124,10 +128,8 @@ void InstructionCodeGeneratorMIPS::VisitVecExtractScalar(HVecExtractScalar* inst break; case DataType::Type::kInt64: DCHECK_EQ(2u, instruction->GetVectorLength()); - __ Mfc1(locations->Out().AsRegisterPairLow<Register>(), - locations->InAt(0).AsFpuRegister<FRegister>()); - __ MoveFromFpuHigh(locations->Out().AsRegisterPairHigh<Register>(), - locations->InAt(0).AsFpuRegister<FRegister>()); + __ Copy_sW(locations->Out().AsRegisterPairLow<Register>(), src, 0); + __ Copy_sW(locations->Out().AsRegisterPairHigh<Register>(), src, 1); break; case DataType::Type::kFloat32: case DataType::Type::kFloat64: @@ -987,10 +989,8 @@ void InstructionCodeGeneratorMIPS::VisitVecSetScalars(HVecSetScalars* instructio break; case DataType::Type::kInt64: DCHECK_EQ(2u, instruction->GetVectorLength()); - __ Mtc1(locations->InAt(0).AsRegisterPairLow<Register>(), - locations->Out().AsFpuRegister<FRegister>()); - __ MoveToFpuHigh(locations->InAt(0).AsRegisterPairHigh<Register>(), - locations->Out().AsFpuRegister<FRegister>()); + __ InsertW(dst, locations->InAt(0).AsRegisterPairLow<Register>(), 0); + __ InsertW(dst, locations->InAt(0).AsRegisterPairHigh<Register>(), 1); break; default: LOG(FATAL) << "Unsupported SIMD type"; |