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| author | Goran Jakovljevic <goran.jakovljevic@mips.com> | 2017-12-14 10:25:20 +0100 |
|---|---|---|
| committer | Goran Jakovljevic <goran.jakovljevic@mips.com> | 2017-12-15 17:33:12 +0100 |
| commit | e7de5ec3e4cd1d607b647d98ea64df105479b867 (patch) | |
| tree | d692c4d1dee08eea4beffd71bd8cdf1d106c059e /compiler/optimizing/code_generator_mips64.h | |
| parent | bee510c94560703102ca553a08ec47119959c204 (diff) | |
| download | art-e7de5ec3e4cd1d607b647d98ea64df105479b867.tar.gz art-e7de5ec3e4cd1d607b647d98ea64df105479b867.tar.bz2 art-e7de5ec3e4cd1d607b647d98ea64df105479b867.zip | |
MIPS: Support swaps between 128-bit locations
Add support for swaps between two SIMDStackSlots, two
VectorRegisters (extended FpuRegister) and between a
SIMDStackSlot and a VectorRegister.
This fixes test 623-checker-loop-regressions for
MIPS64R6 and MIPS32R6.
Test: ./testrunner.py --optimizing --target in QEMU (MIPS64R6)
Test: ./testrunner.py --optimizing --target in QEMU (MIPS32R6)
Change-Id: I36aa209f79790fb6c08b9a171f810769a6b40afc
Diffstat (limited to 'compiler/optimizing/code_generator_mips64.h')
| -rw-r--r-- | compiler/optimizing/code_generator_mips64.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/compiler/optimizing/code_generator_mips64.h b/compiler/optimizing/code_generator_mips64.h index 2a95b3775d..d479410f07 100644 --- a/compiler/optimizing/code_generator_mips64.h +++ b/compiler/optimizing/code_generator_mips64.h @@ -142,6 +142,7 @@ class ParallelMoveResolverMIPS64 : public ParallelMoveResolverWithSwap { void RestoreScratch(int reg) OVERRIDE; void Exchange(int index1, int index2, bool double_slot); + void ExchangeQuadSlots(int index1, int index2); Mips64Assembler* GetAssembler() const; |