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| author | Alexey Frunze <Alexey.Frunze@imgtec.com> | 2016-12-22 13:54:23 -0800 |
|---|---|---|
| committer | Alexey Frunze <Alexey.Frunze@imgtec.com> | 2016-12-22 16:42:01 -0800 |
| commit | c378980e32f0ec9ab7f1d0b87e1d5b97c1f3972c (patch) | |
| tree | 11023f47469b9042091197ea3d2b5fb6e32cfb9e /compiler/optimizing/code_generator_mips64.h | |
| parent | 07001c8540718117b91e8137804fa94d35cbb37a (diff) | |
| download | art-c378980e32f0ec9ab7f1d0b87e1d5b97c1f3972c.tar.gz art-c378980e32f0ec9ab7f1d0b87e1d5b97c1f3972c.tar.bz2 art-c378980e32f0ec9ab7f1d0b87e1d5b97c1f3972c.zip | |
MIPS64: Align register spills on 8-byte boundaries in slow paths
64-bit loads/stores would otherwise be split into pairs of
32-bit ones.
Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU
Test: test-art-target-run-test-optimizing (MIPS64R6) in QEMU
Change-Id: I4846d11b52b71507dfd5ca2e27b3f2a5befcc58e
Diffstat (limited to 'compiler/optimizing/code_generator_mips64.h')
| -rw-r--r-- | compiler/optimizing/code_generator_mips64.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/compiler/optimizing/code_generator_mips64.h b/compiler/optimizing/code_generator_mips64.h index cbd4957e4a..2f71059730 100644 --- a/compiler/optimizing/code_generator_mips64.h +++ b/compiler/optimizing/code_generator_mips64.h @@ -320,6 +320,10 @@ class CodeGeneratorMIPS64 : public CodeGenerator { block_labels_ = CommonInitializeLabels<Mips64Label>(); } + // We prefer aligned loads and stores (less code), so spill and restore registers in slow paths + // at aligned locations. + uint32_t GetPreferredSlotsAlignment() const OVERRIDE { return kMips64DoublewordSize; } + void Finalize(CodeAllocator* allocator) OVERRIDE; // Code generation helpers. |