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path: root/drivers/gpu/drm/nouveau/nv50_fifo.c
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* drm/nv50: import new vm codeBen Skeggs2010-12-081-1/+2
* drm/nouveau: make fifo.create_context() responsible for mapping control regsBen Skeggs2010-12-081-0/+9
* drm/nouveau: move PFIFO ISR into nv04_fifo.cBen Skeggs2010-12-031-0/+4
* drm/nouveau: Refactor context destruction to avoid a lock ordering issue.Francisco Jerez2010-12-031-0/+17
* drm/nouveau: add more fine-grained locking to channel list + structuresBen Skeggs2010-12-031-4/+5
* drm/nv50: implement possible workaround for NV86 PGRAPH TLB flush hangBen Skeggs2010-11-181-0/+5
* drm/nouveau: tidy ram{ht,fc,ro} a bitBen Skeggs2010-09-241-1/+1
* drm/nouveau: remove nouveau_gpuobj_ref completely, replace with sanityBen Skeggs2010-09-241-43/+42
* drm/nouveau: rebase per-channel pramin heap offsets to 0Ben Skeggs2010-09-241-8/+8
* drm/nouveau: modify object accessors, offset in bytes rather than dwordsBen Skeggs2010-09-241-105/+106
* drm/nv50: fix RAMHT sizeBen Skeggs2010-07-131-1/+3
* drm/nv50: cleanup nv50_fifo.cBen Skeggs2010-07-131-67/+40
* drm/nouveau: add instmem flush() hookBen Skeggs2010-07-131-12/+3
* drm/nv50: switch to indirect push buffer controlsBen Skeggs2010-02-251-4/+4
* drm/nouveau: protect channel create/destroy and irq handler with a spinlockMaarten Maathuis2010-02-251-0/+5
* drm/nv50: delete ramfc object after disabling fifo, not beforeMaarten Maathuis2010-02-101-3/+6
* drm/nv50: fix alignment of per-channel fifo cacheBen Skeggs2010-01-181-1/+1
* drm/nv50: restore correct cache1 get/put address on fifoctx loadBen Skeggs2010-01-111-4/+2
* drm/nv50: fix two potential suspend/resume oopsesBen Skeggs2009-12-161-1/+1
* drm/nouveau: Add DRM driver for NVIDIA GPUsBen Skeggs2009-12-111-0/+494
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