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path: root/drivers/gpu/drm/i915/intel_pm.c
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* drm/i915: Clamp efficient frequency to valid rangeTom O'Rourke2015-02-111-1/+4
* drm/i915: Handle CHV in vlv_set_rps_idle()Ville Syrjälä2015-01-301-5/+3
* drm/i915: Use intel_gpu_freq() and intel_freq_opcode()Ville Syrjälä2015-01-271-23/+13
* drm/i915: Add intel_gpu_freq() and intel_freq_opcode()Ville Syrjälä2015-01-271-12/+18
* drm/i915: Change VLV WIZ hashing mode to 16x4Ville Syrjälä2015-01-271-0/+11
* drm/i915: Drop some more CHV pre-production workaroundsVille Syrjälä2015-01-271-5/+1
* drm/i915/skl: Gen9 coarse power gatingZhe Wang2015-01-271-0/+8
* drm/i915/skl: Retrieve the frequency limitsDamien Lespiau2015-01-271-0/+2
* drm/i915/skl: add turbo supportJesse Barnes2015-01-271-0/+30
* drm/i915: Rename the forcewake get/put functionsMika Kuoppala2015-01-271-13/+12
* drm/i915: Make intel_crtc->config a pointerAnder Conselvan de Oliveira2015-01-271-25/+25
* drm/i915: Embedded struct drm_crtc_state in intel_crtc_stateAnder Conselvan de Oliveira2015-01-271-14/+14
* drm/i915: Rename struct intel_crtc_config to intel_crtc_stateAnder Conselvan de Oliveira2015-01-271-1/+1
* Revert "Revert "drm/i915/chv: Use timeout mode for RC6 on chv""Ville Syrjälä2015-01-271-2/+3
* drm/i915: Configure GEN6_RP_DOWN_TIMEOUT on CHVVille Syrjälä2015-01-271-0/+1
* drm/i915: Change VLV GEN6_RP_DOWN_TIMEOUT value to decimalVille Syrjälä2015-01-271-1/+1
* drm/i915: Disable RC6 before configuring in on VLV/CHVVille Syrjälä2015-01-271-0/+6
* drm/i915: New offset for reading frequencies on CHV.Deepak S2015-01-271-7/+47
* Merge tag 'drm-intel-next-2015-01-17' of git://anongit.freedesktop.org/drm-in...Dave Airlie2015-01-271-3/+6
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| * Revert "drm/i915/chv: Use timeout mode for RC6 on chv"Rodrigo Vivi2015-01-131-3/+2
| * Merge tag 'topic/i915-hda-componentized-2015-01-12' into drm-intel-next-queuedDaniel Vetter2015-01-121-12/+22
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| * | drm/i915: Make sample_c messages go faster on Haswell.Kenneth Graunke2015-01-061-0/+4
* | | Merge remote-tracking branch 'origin/master' into drm-nextDave Airlie2015-01-221-11/+3
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| * | | drm/i915: vlv: sanitize RPS interrupt mask during GPU idlingImre Deak2015-01-121-1/+2
| * | | drm/i915: fix HW lockup due to missing RPS IRQ workaround on GEN6Imre Deak2015-01-121-10/+1
| * | | drm/i915: gen9: fix RPS interrupt routing to CPU vs. GTImre Deak2015-01-121-1/+1
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* | | Merge tag 'drm-intel-next-2014-12-19' of git://anongit.freedesktop.org/drm-in...Dave Airlie2015-01-101-792/+25
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| * drm/i915/chv: Use timeout mode for RC6 on chvDeepak S2014-12-161-2/+3
| * drm/i915/skl: Correcting the flushing of pipeSonika Jindal2014-12-151-2/+1
| * drm/i915/skl: Correctly updating sprite wm parameterSonika Jindal2014-12-151-1/+2
| * drm/i915: Move FBC stuff to intel_fbc.cRodrigo Vivi2014-12-101-650/+1
| * drm/i915: Convert pxvid to extvid lookup table to a functionMika Kuoppala2014-12-031-137/+18
* | drm/i915: sanitize RPS resetting during GPU resetImre Deak2014-12-151-9/+19
* | drm/i915/bdw: Fix the write setting up the WIZ hashing modeDamien Lespiau2014-12-101-3/+3
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* drm/i915: remove the IRQs enabled WARN from intel_disable_gt_powersaveImre Deak2014-11-201-3/+0
* drm/i915: vlv: increase timeout when setting idle GPU freqImre Deak2014-11-201-1/+1
* drm/i915: Update ring freq for full gpu freq rangeTom O'Rourke2014-11-201-2/+2
* drm/i915: change initial rps frequency for gen8Tom O'Rourke2014-11-201-1/+2
* drm/i915: Keep min freq above floor on HSW/BDWTom O'Rourke2014-11-201-1/+2
* drm/i915: Use efficient frequency for HSW/BDWTom O'Rourke2014-11-201-14/+32
* Merge tag 'drm-intel-fixes-2014-11-19' into drm-intel-next-queuedDaniel Vetter2014-11-191-5/+0
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| * drm/i915: drop WaSetupGtModeTdRowDispatch:snbDaniel Vetter2014-11-171-5/+0
* | drm/i915: disable rps irqs earlier during suspend/unloadImre Deak2014-11-191-3/+0
* | drm/i915: sanitize rps irq disablingImre Deak2014-11-191-8/+9
* | drm/i915: sanitize rps irq enablingImre Deak2014-11-191-8/+11
* | drm/i915: move rps irq disable one level upImre Deak2014-11-191-6/+8
* | drm/i915: Extend pcode mailbox interfaceTom O'Rourke2014-11-191-2/+2
* | drm/i915: Change CHV SKU400 GPU freq divider to 10Ville Syrjälä2014-11-171-1/+2
* | drm/i915: Add missing newline to 'DDR speed' debug messagesVille Syrjälä2014-11-171-2/+2
* | drm/i915: Refactor vlv/chv GPU frequency divider setupVille Syrjälä2014-11-171-69/+35
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