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path: root/arch/mips/include/asm/mach-sibyte/war.h
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* MIPS: Remove mach-*/war.hThomas Bogendoerfer2020-09-071-11/+0
* MIPS: Get rid of BCM1250_M3_WARThomas Bogendoerfer2020-09-071-14/+0
* MIPS: Replace SIBYTE_1956_WAR by CONFIG_SB1_PASS_2_WORKAROUNDSThomas Bogendoerfer2020-09-071-2/+0
* MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config optionThomas Bogendoerfer2020-09-071-2/+0
* MIPS: Convert R10000_LLSC_WAR info a config optionThomas Bogendoerfer2020-09-071-1/+0
* MIPS: Convert ICACHE_REFILLS_WORKAROUND_WAR into a config optionThomas Bogendoerfer2020-09-071-1/+0
* MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config optionThomas Bogendoerfer2020-09-071-1/+0
* MIPS: Remove MIPS4K_ICACHE_REFILL_WAR and MIPS_CACHE_SYNC_WARThomas Bogendoerfer2020-09-071-2/+0
* MIPS: Convert R4600_V2_HIT_CACHEOP into a config optionThomas Bogendoerfer2020-09-071-2/+0
* MIPS: Convert R4600_V1_HIT_CACHEOP into a config optionThomas Bogendoerfer2020-09-071-1/+0
* MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config optionThomas Bogendoerfer2020-09-071-1/+0
* MIPS: Remove unused R5432_CP0_INTERRUPT_WARPaul Burton2019-07-231-1/+0
* MIPS: SB1: Remove support for Pass 1 parts.Ralf Baechle2015-07-141-2/+1
* MIPS: Whitespace cleanup.Ralf Baechle2013-02-011-2/+2
* MIPS: PMC-Sierra Yosemite: Remove support.Ralf Baechle2012-12-131-1/+0
* MIPS: Sibyte: Apply M3 workaround only on affected chip types and versions.Ralf Baechle2010-04-121-1/+5
* MIPS: Move headfiles to new location below arch/mips/includeRalf Baechle2008-10-111-0/+37
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