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| author | Ingo Molnar <mingo@kernel.org> | 2015-10-12 09:51:18 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2015-10-12 09:51:18 +0200 |
| commit | b9f27c0f4f7db9e5a4ba59228442a75d3177470c (patch) | |
| tree | 49ab61b7e06a5a592f3541e84d1b5908a1d8030f /sound/soc/dwc/designware_i2s.c | |
| parent | 9fc4468d546b6eb55b0aa5b04b0c36238ebf57e7 (diff) | |
| parent | 25cb62b76430a91cc6195f902e61c2cb84ade622 (diff) | |
| download | kernel_replicant_linux-b9f27c0f4f7db9e5a4ba59228442a75d3177470c.tar.gz kernel_replicant_linux-b9f27c0f4f7db9e5a4ba59228442a75d3177470c.tar.bz2 kernel_replicant_linux-b9f27c0f4f7db9e5a4ba59228442a75d3177470c.zip | |
Merge tag 'v4.3-rc5' into timers/core, to pick up fixes before applying new changes
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'sound/soc/dwc/designware_i2s.c')
| -rw-r--r-- | sound/soc/dwc/designware_i2s.c | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/sound/soc/dwc/designware_i2s.c b/sound/soc/dwc/designware_i2s.c index a3e97b46b64e..ba34252b7bba 100644 --- a/sound/soc/dwc/designware_i2s.c +++ b/sound/soc/dwc/designware_i2s.c @@ -131,23 +131,32 @@ static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream) if (stream == SNDRV_PCM_STREAM_PLAYBACK) { for (i = 0; i < 4; i++) - i2s_write_reg(dev->i2s_base, TOR(i), 0); + i2s_read_reg(dev->i2s_base, TOR(i)); } else { for (i = 0; i < 4; i++) - i2s_write_reg(dev->i2s_base, ROR(i), 0); + i2s_read_reg(dev->i2s_base, ROR(i)); } } static void i2s_start(struct dw_i2s_dev *dev, struct snd_pcm_substream *substream) { - + u32 i, irq; i2s_write_reg(dev->i2s_base, IER, 1); - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + for (i = 0; i < 4; i++) { + irq = i2s_read_reg(dev->i2s_base, IMR(i)); + i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30); + } i2s_write_reg(dev->i2s_base, ITER, 1); - else + } else { + for (i = 0; i < 4; i++) { + irq = i2s_read_reg(dev->i2s_base, IMR(i)); + i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03); + } i2s_write_reg(dev->i2s_base, IRER, 1); + } i2s_write_reg(dev->i2s_base, CER, 1); } |