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| author | Thomas Gleixner <tglx@linutronix.de> | 2017-02-09 14:43:08 +0100 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2017-02-09 14:43:08 +0100 |
| commit | b4f2d7c3424c00de162c042a5a3a5ed19974677c (patch) | |
| tree | 2783d3212e82f01b53bfb0a408d901918870782e /drivers/pci/probe.c | |
| parent | 788d23930a9724fc85cdf9999521a867d8748019 (diff) | |
| parent | 34d677a90f0682a26327dbefc0db1cf81647e7bc (diff) | |
| download | kernel_replicant_linux-b4f2d7c3424c00de162c042a5a3a5ed19974677c.tar.gz kernel_replicant_linux-b4f2d7c3424c00de162c042a5a3a5ed19974677c.tar.bz2 kernel_replicant_linux-b4f2d7c3424c00de162c042a5a3a5ed19974677c.zip | |
Merge tag 'irqchip-for-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core
Pull irqchip updates for 4.11 from Marc Zyngier
- A number of gic-v3-its cleanups and fixes
- A fix for the MIPS GIC
- One new interrupt controller for the Cortina Gemini platform
- Support for the Qualcomm interrupt combiner, together with
its ACPI goodness
Diffstat (limited to 'drivers/pci/probe.c')
| -rw-r--r-- | drivers/pci/probe.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index e164b5c9f0f0..204960e70333 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1169,6 +1169,7 @@ void set_pcie_port_type(struct pci_dev *pdev) pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); if (!pos) return; + pdev->pcie_cap = pos; pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); pdev->pcie_flags_reg = reg16; @@ -1176,13 +1177,14 @@ void set_pcie_port_type(struct pci_dev *pdev) pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; /* - * A Root Port is always the upstream end of a Link. No PCIe - * component has two Links. Two Links are connected by a Switch - * that has a Port on each Link and internal logic to connect the - * two Ports. + * A Root Port or a PCI-to-PCIe bridge is always the upstream end + * of a Link. No PCIe component has two Links. Two Links are + * connected by a Switch that has a Port on each Link and internal + * logic to connect the two Ports. */ type = pci_pcie_type(pdev); - if (type == PCI_EXP_TYPE_ROOT_PORT) + if (type == PCI_EXP_TYPE_ROOT_PORT || + type == PCI_EXP_TYPE_PCIE_BRIDGE) pdev->has_secondary_link = 1; else if (type == PCI_EXP_TYPE_UPSTREAM || type == PCI_EXP_TYPE_DOWNSTREAM) { |