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| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2018-10-15 19:35:17 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2018-10-16 09:01:00 -0700 |
| commit | 4e53840fdfdd054f645a03fa27f79296fa0d5d15 (patch) | |
| tree | 51fd6a5c120c5bee4e6d14193c6f449d8f2ec2bc /drivers/hwmon/coretemp.c | |
| parent | d72e84ccba2068608a7fde587ed887ece46aa55b (diff) | |
| download | kernel_replicant_linux-4e53840fdfdd054f645a03fa27f79296fa0d5d15.tar.gz kernel_replicant_linux-4e53840fdfdd054f645a03fa27f79296fa0d5d15.tar.bz2 kernel_replicant_linux-4e53840fdfdd054f645a03fa27f79296fa0d5d15.zip | |
drm/i915/icl: Introduce new macros to get combophy registers
combo-phy register instances are at same offset from base for each
combo-phy port, i.e.
Port A base offset: 0x16200
Port B base offset: 0x6C000
All the other addresses for both ports can be derived by calculating
offset to these base addresses.
PORT_CL_DW_OFFSET 0x0
PORT_CL_DW<x> 0 + x * 4
PORT_COMP_OFFSET 0x100
PORT_COMP_DW<x> 0x100 + x * 4
PORT_PCS_AUX_OFFSET 0x300
PORT_PCS_GRP_OFFSET 0x600
PORT_PCS_LN<y>_OFFSET 0x800 + y * 0x100
PORT_TX_AUX_OFFSET 0x380
PORT_TX_GRP_OFFSET 0x680
PORT_TX_LN<y>_OFFSET 0x880 + y * 0x100
And inside each PORT_TX_[AUX|GRP|LN] we add `dw * 4`.
Based on original patch by Mahesh Kumar <mahesh1.kumar@intel.com>.
v2: make port, dw and ln arguments follow the order in
register's name
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181016023517.8576-1-lucas.demarchi@intel.com
Diffstat (limited to 'drivers/hwmon/coretemp.c')
0 files changed, 0 insertions, 0 deletions