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| author | Eric Anholt <eric@anholt.net> | 2018-11-28 15:09:25 -0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2018-11-30 13:03:32 -0800 |
| commit | 1584f16ca96ef124aad79efa3303cff5f3530e2c (patch) | |
| tree | b97a53e848d737236e73a238fe86788c5a42da5b /drivers/gpu/drm/v3d/v3d_irq.c | |
| parent | 1d8224e790c7f9d0091a299b985c76ba0b229f43 (diff) | |
| download | kernel_replicant_linux-1584f16ca96ef124aad79efa3303cff5f3530e2c.tar.gz kernel_replicant_linux-1584f16ca96ef124aad79efa3303cff5f3530e2c.tar.bz2 kernel_replicant_linux-1584f16ca96ef124aad79efa3303cff5f3530e2c.zip | |
drm/v3d: Add support for submitting jobs to the TFU.
The TFU can copy from raster, UIF, and SAND input images to UIF output
images, with optional mipmap generation. This will certainly be
useful for media EGL image input, but is also useful immediately for
mipmap generation without bogging the V3D core down.
For now we only run the queue 1 job deep, and don't have any hang
recovery (though I don't think we should need it, with TFU). Queuing
multiple jobs in the HW will require synchronizing the YUV coefficient
regs updates since they don't get FIFOed with the job.
v2: Change the ioctl to IOW instead of IOWR, always set COEF0, explain
why TFU is AUTH, clarify the syncing docs, drop the unused TFU
interrupt regs (you're expected to use the hub's), don't take
&bo->base for NULL bos.
v3: Fix a little whitespace alignment (noticed by checkpatch), rebase
on drm_sched_job_cleanup() changes.
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Dave Emett <david.emett@broadcom.com> (v2)
Link: https://patchwork.freedesktop.org/patch/264607/
Diffstat (limited to 'drivers/gpu/drm/v3d/v3d_irq.c')
| -rw-r--r-- | drivers/gpu/drm/v3d/v3d_irq.c | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/drivers/gpu/drm/v3d/v3d_irq.c b/drivers/gpu/drm/v3d/v3d_irq.c index e07514eb11b5..dd7a7b0bd5a1 100644 --- a/drivers/gpu/drm/v3d/v3d_irq.c +++ b/drivers/gpu/drm/v3d/v3d_irq.c @@ -4,8 +4,8 @@ /** * DOC: Interrupt management for the V3D engine * - * When we take a binning or rendering flush done interrupt, we need - * to signal the fence for that job so that the scheduler can queue up + * When we take a bin, render, or TFU done interrupt, we need to + * signal the fence for that job so that the scheduler can queue up * the next one and unblock any waiters. * * When we take the binner out of memory interrupt, we need to @@ -23,7 +23,8 @@ #define V3D_HUB_IRQS ((u32)(V3D_HUB_INT_MMU_WRV | \ V3D_HUB_INT_MMU_PTI | \ - V3D_HUB_INT_MMU_CAP)) + V3D_HUB_INT_MMU_CAP | \ + V3D_HUB_INT_TFUC)) static void v3d_overflow_mem_work(struct work_struct *work) @@ -117,6 +118,11 @@ v3d_hub_irq(int irq, void *arg) /* Acknowledge the interrupts we're handling here. */ V3D_WRITE(V3D_HUB_INT_CLR, intsts); + if (intsts & V3D_HUB_INT_TFUC) { + dma_fence_signal(v3d->tfu_job->done_fence); + status = IRQ_HANDLED; + } + if (intsts & (V3D_HUB_INT_MMU_WRV | V3D_HUB_INT_MMU_PTI | V3D_HUB_INT_MMU_CAP)) { |