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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2016-04-09 10:57:56 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2016-04-09 12:09:45 +0100 |
| commit | 0d317ce99e226a338fe0962e711795c6a8ed2cb2 (patch) | |
| tree | f31c16fbb3c4578c50af6c3a3d95519f1a3d12cc /drivers/gpu/drm/i915/intel_ringbuffer.h | |
| parent | 12471ba87a08bd1dd0aac18015d7782e02ea02de (diff) | |
| download | kernel_replicant_linux-0d317ce99e226a338fe0962e711795c6a8ed2cb2.tar.gz kernel_replicant_linux-0d317ce99e226a338fe0962e711795c6a8ed2cb2.tar.bz2 kernel_replicant_linux-0d317ce99e226a338fe0962e711795c6a8ed2cb2.zip | |
drm/i915: Use simplest form for flushing the single cacheline in the HWS
Rather than call a function to compute the matching cachelines and
clflush them, just call the clflush *instruction* directly. We also know
that we can use the unpatched plain clflush rather than the clflushopt
alternative.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1460195877-20520-4-git-send-email-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.h')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 29c54cc1ee5c..9d7b7bf9ed14 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -385,8 +385,9 @@ intel_ring_sync_index(struct intel_engine_cs *engine, static inline void intel_flush_status_page(struct intel_engine_cs *engine, int reg) { - drm_clflush_virt_range(&engine->status_page.page_addr[reg], - sizeof(uint32_t)); + mb(); + clflush(&engine->status_page.page_addr[reg]); + mb(); } static inline u32 |