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| author | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2020-02-07 17:47:43 -0800 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2020-02-07 17:47:43 -0800 |
| commit | c0f00d270eba3cba688dd62a7b1a742ad289b879 (patch) | |
| tree | cea3939f9834a67d1fce2d9e74d5125f56167639 /drivers/gpu/drm/i915/gvt/handlers.c | |
| parent | 5ba32c7be81e53ea8a27190b0f6be98e6c6779af (diff) | |
| parent | 9f880327160feb695de03caa29604883b0d00087 (diff) | |
| download | kernel_replicant_linux-c0f00d270eba3cba688dd62a7b1a742ad289b879.tar.gz kernel_replicant_linux-c0f00d270eba3cba688dd62a7b1a742ad289b879.tar.bz2 kernel_replicant_linux-c0f00d270eba3cba688dd62a7b1a742ad289b879.zip | |
Merge drm/drm-next into drm-intel-next-queued
Moving the base forward since this one was so old.
New base contains fixes that we needed.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/handlers.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/handlers.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index fa411ee08a9d..ae6700dc9d73 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -341,6 +341,10 @@ static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); engine_mask |= BIT(VCS1); } + if (data & GEN9_GRDOM_GUC) { + gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id); + vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; + } engine_mask &= INTEL_INFO(vgpu->gvt->dev_priv)->engine_mask; } @@ -1636,6 +1640,16 @@ static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu, return 0; } +static int guc_status_read(struct intel_vgpu *vgpu, + unsigned int offset, void *p_data, + unsigned int bytes) +{ + /* keep MIA_IN_RESET before clearing */ + read_vreg(vgpu, offset, p_data, bytes); + vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET; + return 0; +} + static int mmio_read_from_hw(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { @@ -2672,6 +2686,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); + MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL); + return 0; } |