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| author | Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | 2018-04-27 16:34:37 -0500 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2018-05-06 12:49:15 +0200 |
| commit | 68091ee7ac3c1a8786fe1bebbd616b14236efb99 (patch) | |
| tree | 368d443c105928aba52b17c236f376bf048d8f62 /arch/x86/include | |
| parent | 1d200c078d0e3e49e2995b9d25fef8926d491f4f (diff) | |
| download | kernel_replicant_linux-68091ee7ac3c1a8786fe1bebbd616b14236efb99.tar.gz kernel_replicant_linux-68091ee7ac3c1a8786fe1bebbd616b14236efb99.tar.bz2 kernel_replicant_linux-68091ee7ac3c1a8786fe1bebbd616b14236efb99.zip | |
x86/CPU/AMD: Calculate last level cache ID from number of sharing threads
Last Level Cache ID can be calculated from the number of threads sharing
the cache, which is available from CPUID Fn0x8000001D (Cache Properties).
This is used to left-shift the APIC ID to derive LLC ID.
Therefore, default to this method unless the APIC ID enumeration does not
follow the scheme.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1524864877-111962-5-git-send-email-suravee.suthikulpanit@amd.com
Diffstat (limited to 'arch/x86/include')
| -rw-r--r-- | arch/x86/include/asm/cacheinfo.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/x86/include/asm/cacheinfo.h b/arch/x86/include/asm/cacheinfo.h new file mode 100644 index 000000000000..e958e28f7ab5 --- /dev/null +++ b/arch/x86/include/asm/cacheinfo.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_CACHEINFO_H +#define _ASM_X86_CACHEINFO_H + +void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id); + +#endif /* _ASM_X86_CACHEINFO_H */ |