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| author | Dan Williams <dan.j.williams@intel.com> | 2009-04-08 14:28:13 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2009-04-08 14:28:13 -0700 |
| commit | fd74ea65883c7e6903e9b652795f72b723a2be69 (patch) | |
| tree | 0792ad598080eae201d2836ac3c5a8fc46d0d03e /arch/mips/mm/page.c | |
| parent | c8f517c444e4f9f55b5b5ca202b8404691a35805 (diff) | |
| parent | 8c6db1bbf80123839ec87bdd6cb364aea384623d (diff) | |
| download | kernel_replicant_linux-fd74ea65883c7e6903e9b652795f72b723a2be69.tar.gz kernel_replicant_linux-fd74ea65883c7e6903e9b652795f72b723a2be69.tar.bz2 kernel_replicant_linux-fd74ea65883c7e6903e9b652795f72b723a2be69.zip | |
Merge branch 'dmaengine' into async-tx-raid6
Diffstat (limited to 'arch/mips/mm/page.c')
| -rw-r--r-- | arch/mips/mm/page.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c index 1417c6494858..48060c635acd 100644 --- a/arch/mips/mm/page.c +++ b/arch/mips/mm/page.c @@ -172,8 +172,9 @@ static void __cpuinit set_prefetch_parameters(void) */ cache_line_size = cpu_dcache_line_size(); switch (current_cpu_type()) { + case CPU_R5500: case CPU_TX49XX: - /* TX49 supports only Pref_Load */ + /* These processors only support the Pref_Load. */ pref_bias_copy_load = 256; break; |