diff options
| author | Paul Burton <paul.burton@imgtec.com> | 2017-08-12 19:49:31 -0700 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2017-08-30 00:57:26 +0200 |
| commit | 846e1913f5ccf3fb822a7aa166e5a840c8bdc61b (patch) | |
| tree | b4ffc6ee44b019c5515ec237b099cfa32d867ddf /arch/mips/kernel | |
| parent | ed7eb5aad7d4e4945fac664c9b67d0db2a8a3db8 (diff) | |
| download | kernel_replicant_linux-846e1913f5ccf3fb822a7aa166e5a840c8bdc61b.tar.gz kernel_replicant_linux-846e1913f5ccf3fb822a7aa166e5a840c8bdc61b.tar.bz2 kernel_replicant_linux-846e1913f5ccf3fb822a7aa166e5a840c8bdc61b.zip | |
MIPS: CPS: Use change_*, set_* & clear_* where appropriate
Make use of the new change_*, set_* & clear_* accessor functions for CPS
(CM, CPC & GIC) registers where doing so makes the code easier to read
or shortens it without adversely affecting readability.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17005/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel')
| -rw-r--r-- | arch/mips/kernel/mips-cm.c | 4 | ||||
| -rw-r--r-- | arch/mips/kernel/smp-cps.c | 6 |
2 files changed, 3 insertions, 7 deletions
diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c index 91b861ebc907..497dbb128438 100644 --- a/arch/mips/kernel/mips-cm.c +++ b/arch/mips/kernel/mips-cm.c @@ -233,9 +233,7 @@ int mips_cm_probe(void) } /* set default target to memory */ - base_reg &= ~CM_GCR_BASE_CMDEFTGT; - base_reg |= CM_GCR_BASE_CMDEFTGT_MEM; - write_gcr_base(base_reg); + change_gcr_base(CM_GCR_BASE_CMDEFTGT, CM_GCR_BASE_CMDEFTGT_MEM); /* disable CM regions */ write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR); diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index 777e0193e8ed..5729d2c77461 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -212,7 +212,7 @@ err_out: static void boot_core(unsigned int core, unsigned int vpe_id) { - u32 access, stat, seq_state; + u32 stat, seq_state; unsigned timeout; /* Select the appropriate core */ @@ -228,9 +228,7 @@ static void boot_core(unsigned int core, unsigned int vpe_id) write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB); /* Ensure the core can access the GCRs */ - access = read_gcr_access(); - access |= 1 << core; - write_gcr_access(access); + set_gcr_access(1 << core); if (mips_cpc_present()) { /* Reset the core */ |