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| author | James Morris <james.l.morris@oracle.com> | 2012-09-28 13:37:32 +1000 |
|---|---|---|
| committer | James Morris <james.l.morris@oracle.com> | 2012-09-28 13:37:32 +1000 |
| commit | bf5308344527d015ac9a6d2bda4ad4d40fd7d943 (patch) | |
| tree | 566e61e2cfc648c374d15cfc8c661b73e1a471f8 /arch/c6x/include/asm/cache.h | |
| parent | 3585e96cd1049682b8a19a0b699422156e9d735b (diff) | |
| parent | 979570e02981d4a8fc20b3cc8fd651856c98ee9d (diff) | |
| download | kernel_replicant_linux-bf5308344527d015ac9a6d2bda4ad4d40fd7d943.tar.gz kernel_replicant_linux-bf5308344527d015ac9a6d2bda4ad4d40fd7d943.tar.bz2 kernel_replicant_linux-bf5308344527d015ac9a6d2bda4ad4d40fd7d943.zip | |
Merge tag 'v3.6-rc7' into next
Linux 3.6-rc7
Requested by David Howells so he can merge his key susbsystem work into
my tree with requisite -linus changesets.
Diffstat (limited to 'arch/c6x/include/asm/cache.h')
| -rw-r--r-- | arch/c6x/include/asm/cache.h | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/arch/c6x/include/asm/cache.h b/arch/c6x/include/asm/cache.h index 6d521d96d941..09c5a0f5f4d1 100644 --- a/arch/c6x/include/asm/cache.h +++ b/arch/c6x/include/asm/cache.h @@ -1,7 +1,7 @@ /* * Port on Texas Instruments TMS320C6x architecture * - * Copyright (C) 2005, 2006, 2009, 2010 Texas Instruments Incorporated + * Copyright (C) 2005, 2006, 2009, 2010, 2012 Texas Instruments Incorporated * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com) * * This program is free software; you can redistribute it and/or modify @@ -16,9 +16,14 @@ /* * Cache line size */ -#define L1D_CACHE_BYTES 64 -#define L1P_CACHE_BYTES 32 -#define L2_CACHE_BYTES 128 +#define L1D_CACHE_SHIFT 6 +#define L1D_CACHE_BYTES (1 << L1D_CACHE_SHIFT) + +#define L1P_CACHE_SHIFT 5 +#define L1P_CACHE_BYTES (1 << L1P_CACHE_SHIFT) + +#define L2_CACHE_SHIFT 7 +#define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT) /* * L2 used as cache @@ -29,7 +34,8 @@ * For practical reasons the L1_CACHE_BYTES defines should not be smaller than * the L2 line size */ -#define L1_CACHE_BYTES L2_CACHE_BYTES +#define L1_CACHE_SHIFT L2_CACHE_SHIFT +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) #define L2_CACHE_ALIGN_LOW(x) \ (((x) & ~(L2_CACHE_BYTES - 1))) |