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| author | Will Deacon <will.deacon@arm.com> | 2015-10-06 18:46:29 +0100 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2015-10-07 11:56:33 +0100 |
| commit | 28c6fbc3b446caf5f8d1f2d7b79e09e743158a4d (patch) | |
| tree | a5c5a5a1f55820295ab1c9cf53a41217e4430373 /arch/arm64/include/asm/tlbflush.h | |
| parent | 38d96287504a2478eb538bfecfa1fddd743bb6b2 (diff) | |
| download | kernel_replicant_linux-28c6fbc3b446caf5f8d1f2d7b79e09e743158a4d.tar.gz kernel_replicant_linux-28c6fbc3b446caf5f8d1f2d7b79e09e743158a4d.tar.bz2 kernel_replicant_linux-28c6fbc3b446caf5f8d1f2d7b79e09e743158a4d.zip | |
arm64: tlb: remove redundant barrier from __flush_tlb_pgtable
__flush_tlb_pgtable is used to invalidate intermediate page table
entries after they have been cleared and are about to be freed. Since
pXd_clear imply memory barriers, we don't need the extra one here.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/tlbflush.h')
| -rw-r--r-- | arch/arm64/include/asm/tlbflush.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index 93e9f964805c..b460ae28e346 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -163,7 +163,6 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm, { unsigned long addr = uaddr >> 12 | (ASID(mm) << 48); - dsb(ishst); asm("tlbi vae1is, %0" : : "r" (addr)); dsb(ish); } |