diff options
| author | Angelo Dureghello <angelo@kernel-space.org> | 2021-03-16 00:15:10 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2021-03-30 14:31:59 +0200 |
| commit | af3e6c3dcf5407ef98acd51c9faa727ed25e15c2 (patch) | |
| tree | 6020c87e9576027e7ef379978ed3d0793c45747f | |
| parent | 0cbadc0fb54ca7fbff1a6c175007bcb1c4b495e8 (diff) | |
| download | kernel_replicant_linux-af3e6c3dcf5407ef98acd51c9faa727ed25e15c2.tar.gz kernel_replicant_linux-af3e6c3dcf5407ef98acd51c9faa727ed25e15c2.tar.bz2 kernel_replicant_linux-af3e6c3dcf5407ef98acd51c9faa727ed25e15c2.zip | |
can: flexcan: flexcan_chip_freeze(): fix chip freeze for missing bitrate
[ Upstream commit 47c5e474bc1e1061fb037d13b5000b38967eb070 ]
For cases when flexcan is built-in, bitrate is still not set at
registering. So flexcan_chip_freeze() generates:
[ 1.860000] *** ZERO DIVIDE *** FORMAT=4
[ 1.860000] Current process id is 1
[ 1.860000] BAD KERNEL TRAP: 00000000
[ 1.860000] PC: [<402e70c8>] flexcan_chip_freeze+0x1a/0xa8
To allow chip freeze, using an hardcoded timeout when bitrate is still
not set.
Fixes: ec15e27cc890 ("can: flexcan: enable RX FIFO after FRZ/HALT valid")
Link: https://lore.kernel.org/r/20210315231510.650593-1-angelo@kernel-space.org
Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
[mkl: use if instead of ? operator]
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
| -rw-r--r-- | drivers/net/can/flexcan.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c index d712c6fdbc87..7cbaac238ff6 100644 --- a/drivers/net/can/flexcan.c +++ b/drivers/net/can/flexcan.c @@ -658,9 +658,15 @@ static int flexcan_chip_disable(struct flexcan_priv *priv) static int flexcan_chip_freeze(struct flexcan_priv *priv) { struct flexcan_regs __iomem *regs = priv->regs; - unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate; + unsigned int timeout; + u32 bitrate = priv->can.bittiming.bitrate; u32 reg; + if (bitrate) + timeout = 1000 * 1000 * 10 / bitrate; + else + timeout = FLEXCAN_TIMEOUT_US / 10; + reg = priv->read(®s->mcr); reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT; priv->write(reg, ®s->mcr); |