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* Convert to Android.bpDan Willemsen2020-04-123-38/+48
| | | | | | | | | | | | See build/soong/README.md for more information about Soong. Removes BOARD_GPU_DRIVERS, which wasn't affecting anything, since none of the HAVE_* macros are defined. Even if they were, we'd prefer to compile all of them so that a single library can support multiple boards. Test: mmma external/libdrm Change-Id: Ie01736bce6cf41e3da5040fe5341ade0634b5111
* intel: sync i915_pciids.h with kernelSwathi Dhanavanthri2020-03-231-2/+6
| | | | | | | | Changes: 3882581753d1 ("drm/i915/tgl: Add new PCI IDs to TGL") Signed-off-by: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com> Reviewed-by: Timo Aaltonen <timo.aaltonen@canonical.com>
* intel: drm_intel_bo_gem_create_from_* on platforms w/o HW tilingImre Deak2020-01-281-16/+27
| | | | | | | | | | | | | | Platforms without a HW detiler doesn't support the get_tiling IOCTL. Fix the drm_intel_bo_gem_create_from_* functions assuming the default no-tiling, no-swizzling setting for the GEM buffer in this case. v2: - Add the missing gem handle IOCTL parameter. (Eric) Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
* intel: sync i915_pciids.h with kernelJosé Roberto de Souza2019-12-171-13/+18
| | | | | | | | | | | | | | | | Changes: 651cc835d5f6 ("drm/i915: Add new EHL/JSL PCI ids") b6a8781a447c ("drm/i915/cml: Remove unsupport PCI ID") 8717c6b7414f ("drm/i915/cml: Separate U series pci id from origianl list.") v2: added the latest CML changes Cc: James Ausmus <james.ausmus@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
* intel: convert to new symbols checkEric Engestrom2019-11-112-23/+8
| | | | Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
* Revert "Revert "libdrm: remove autotools support""Eric Engestrom2019-10-181-75/+0
| | | | | The external tooling issue has been fixed, so we can delete autotools again :)
* Revert "libdrm: remove autotools support"Marek Olšák2019-10-161-0/+75
| | | | This reverts commit f057dc91e93ae21e11ab48a26127d569972f3eae.
* libdrm: remove autotools supportEric Engestrom2019-10-141-75/+0
| | | | | Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
* *-symbols-check: let meson figure out how to execute the scriptsEric Engestrom2019-10-041-14/+8
| | | | Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
* *-symbols-check: use normal shell over bashEmil Velikov2019-10-041-1/+1
| | | | | | | | | | None of the tests are bash specific. Tested with bash, zsh, dash, mksh and ksh. Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Tested-by: Niclas Zeising <zeising@daemonic.se> Reviewed-by: Niclas Zeising <zeising@daemonic.se> Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
* intel: sync i915_pciids.h with kernelAnusha Srivatsa2019-09-061-1/+4
| | | | | | | | | | | | | Add the new CML PCI IDS. Align with kernel commit: bfc4c359b2822 ("drm/i915/cml: Add Missing PCI IDs") This is in sync with kernel header as of: 0747590267e7 ("drm-tip: 2019y-08m-30d-18h-03m-18s UTC integration manifest") Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
* intel: Add support for EHLRodrigo Vivi2019-07-291-0/+1
| | | | | | | | | Add the PCI ID import for EHL. Cc: James Ausmus <james.ausmus@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
* intel: add the TGL 12 PCI IDs and macrosRodrigo Vivi2019-07-292-0/+2
| | | | | | Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
* intel: sync i915_pciids.h with kernelLucas De Marchi2019-07-291-53/+141
| | | | | | | | | Straight copy from the kernel file, aligned with drm-intel-next-queued commit cb823ed9915b ("drm/i915/gt: Use intel_gt as the primary object for handling resets") Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
* fix various typosEric Engestrom2019-04-172-2/+2
| | | | | | | | | | | Saw a couple of typos fixes in the patch DragonFlyBSD carries [1], so I ran codespell (a spell checker for code) on the whole repo. [1] https://github.com/DragonFlyBSD/DPorts/blob/master/graphics/libdrm/files/patch-xf86drm.c Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
* intel: sync i915_pciids.h with kernelAnusha2019-03-251-2/+36
| | | | | | | | | Add CML and EHL PCI IDs, and one more for ICL. This is in sync with kernel header as of b024ab9b2d3a ("drm/i915/bios: iterate over child devices to initialize ddi_port_info") Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
* intel: sync i915_pciids.h with kernelRodrigo Vivi2019-02-041-8/+21
| | | | | | | | | | | | | | | | | | Straight copy from the kernel file. Add more PCI Device IDs for Coffee Lake, Ice Lake, and Amber Lake. It also include a reorg on Whiskey Lake IDs. Align with kernel commits: 5e0f5a58b167 ("drm/i915/cfl: Adding another PCI Device ID.") 03ca3cf8e9aa ("drm/i915/icl: Adding few more device IDs for Ice Lake") c0c46ca461f1 ("drm/i915/aml: Add new Amber Lake PCI ID") c1c8f6fa731b ("drm/i915: Redefine some Whiskey Lake SKUs") Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
* intel: include i915_pciids.h in the tarballEmil Velikov2018-10-041-0/+1
| | | | | | Fixes: 4e81d4f9c9b ("intel: add generic functions to check PCI ID") Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
* *-symbols-check: error out when using unset variablesEmil Velikov2018-10-041-0/+2
| | | | | | | It will make bugs like the one fixed with previous patch dead obvious. Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
* automake: set NM before running the testsEmil Velikov2018-10-041-0/+1
| | | | | | | | | Set/export the NM variable since it may not be set already. Fixes: 4f08bfe96da ("*-symbol-check: Don't hard-code nm executable") Cc: Heiko Becker <heirecka@exherbo.org> Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
* intel: add missing drm_public exportsEric Engestrom2018-09-201-3/+3
| | | | | | | | | | Fixes: 36bb0ea47b71d220b31e "intel: annotate public functions" Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Mark Janes <mark.a.janes@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108006 Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com> Tested-by: Dylan Baker <dylan@pnwbakers.com>
* autotools: make symbols hidden by defaultLucas De Marchi2018-09-191-0/+1
| | | | | | | | Now that symbols that should be exported are annotated accordingly, make all the rest hidden by default. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Eric Engestrom <eric.engestrom@intel.com>
* meson: make symbols hidden by defaultLucas De Marchi2018-09-191-2/+2
| | | | | | | | | Now that symbols that should be exported are annotated accordingly, make all the rest hidden by default. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com> Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
* intel: annotate public functionsLucas De Marchi2018-09-194-81/+80
| | | | | | | | | | | | | | | | | | | This was done with: while read sym; do read f func line _ <<<$(cscope -d -L -1 $sym) if [ ! -z "$f" ]; then line=$((line-1)) sed -i "${line}s/^/drm_public /" $f fi done < /tmp/a.txt Then some corner cases were manually fixed. "a.txt" above contains the symbols collected from intel/intel-symbol-check. The idea here will be to switch the default visibility to hidden so we don't export symbols we shouldn't. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
* intel: annotate the intel genx helpers as privateEmil Velikov2018-09-122-4/+5
| | | | | | | | | | | | | | | | | | They're used internally and never meant to be part of the API. Add the drm_private notation, which should resolve that. v2: (Rodrigo) Add missing include. v3: (Rodrigo) Keep includes grouped per Eric suggestion. Cc: Eric Engestrom <eric.engestrom@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Fixes: 4e81d4f9c9b ("intel: add generic functions to check PCI ID") Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Acked-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
* intel: get gen once for gen >= 9Lucas De Marchi2018-09-052-13/+3
| | | | | | | | | We don't need to call IS_GEN() for each gen >= 9: we can rather use the new intel_is_genx() helper to iterate the pciids array once. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
* intel: make gen9 use generic gen macroLucas De Marchi2018-09-052-186/+6
| | | | | | | | | | The 2 PCI IDs that are used for the command line overrid mechanism were left defined. The rest can be gone and then we just use the kernel defines. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
* intel: make gen10 use generic gen macroLucas De Marchi2018-09-052-33/+2
| | | | | | Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
* intel: make gen11 use generic gen macroLucas De Marchi2018-09-052-25/+3
| | | | | | Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
* intel: add generic functions to check PCI IDLucas De Marchi2018-09-055-2/+549
| | | | | | | | | | | | | | | | | | | | | | | | | | This will allow platforms to reuse kernel IDs instead of manually keeping them in sync. In most of the cases we only need to extend IS_9XX(). Current platforms that fit this requirement can be ported over to use this macro. Right now it's a nop since it doesn't have any PCI ID added. The i915_pciids.h header is in sync with kernel tree on drm-tip 2018y-08m-20d-21h-41m-11s. v2: - move to a separate .c so we can have the array in a single compilation unit - use a single array for all gens - add real functions to get or check gen by pciid - define our own pci device struct rather than inherit the one kernel uses: we can throw away most of the fields v3: - add comment to keep ids sorted by gen - remove misleading comment about all gens Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
* intel: Add a new CFL PCI ID.Rodrigo Vivi2018-08-141-2/+4
| | | | | | | | | | | | | One more CFL ID added to spec. Align with kernel commit d0e062ebb3a4 ("drm/i915/cfl: Add a new CFL PCI ID.") v2: fix commit subject. Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
* intel: Introducing Amber Lake platformJosé Roberto de Souza2018-06-201-3/+6
| | | | | | | | | | | | | | | | | | Amber Lake uses the same gen graphics as Kaby Lake, including a id that were previously marked as reserved on Kaby Lake, but that now is moved to AML page. So, let's just move it to AML macro that will feed into KBL macro just to keep it better organized to make easier future code review but it will be handled as a KBL. This is a copy of merged i915's commit e364672477a1 ("drm/i915/aml: Introducing Amber Lake platform") Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
* intel: Introducing Whiskey Lake platformJosé Roberto de Souza2018-06-201-16/+17
| | | | | | | | | | | | | | | | | | Whiskey Lake uses the same gen graphics as Coffe Lake, including some ids that were previously marked as reserved on Coffe Lake, but that now are moved to WHL page. So, let's just move them to WHL macros that will feed into CFL macro just to keep it better organized to make easier future code review but it will be handled as a CFL. This is a copy of merged i915's commit b9be78531d27 ("drm/i915/whl: Introducing Whiskey Lake platform") Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
* intel: add support for ICL 11Paulo Zanoni2018-05-013-2/+31
| | | | | | | | | | | | | | | | | Add the PCI IDs and the basic code to enable ICL. This is the current PCI ID list in our documentation. Kernel commit: d55cb4fa2cf0 ("drm/i915/icl: Add the ICL PCI IDs") v2: Michel provided a fix to IS_9XX that was broken by rebase bot. v3: Fix double definition of PCI IDs, update IDs according to bspec and keep them in the same order and rebase (Lucas) Cc: Michel Thierry <michel.thierry@intel.com> Reviewed-by: Michel Thierry <michel.thierry@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
* Intel: Add a Kaby Lake PCI IDMatt Atwood2018-04-241-2/+4
| | | | | | | | | | | Based on kernel commit '672e314b21dc ("drm/i915/kbl: Add KBL GT2 sku")' v2: name change M -> ULX, add enumeration in KBL ULX v3: add entry to IS_KABYLAKE Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
* Revert "libdrm: intel/Android.mk: Filter libdrm_intel library requirements ↵Emil Velikov2018-03-281-2/+0
| | | | | | | | | | | | | | | | on x86/x86_64" This reverts commit ed07718ae7bab596297abf210bb0c37c6dba58ed. The commit added a guard since libpciaccess may be missing on some setups. As of last commit there are no traces of the project, from Android POV. Hence, we can revert this workaround - which caused similar breakage to the one it's trying to fix. This time in Mesa. Cc: Rob Herring <rob.herring@linaro.org> Acked-by: John Stultz <john.stultz@linaro.org>
* intel: Do not use libpciaccess on AndroidTomasz Figa2018-03-282-2/+13
| | | | | | | | | | | | | | This patch makes the code not rely anymore on libpciaccess when compiled for Android to eliminate ioperm() and iopl() syscalls required by that library. As a side effect, the mappable aperture size is hardcoded to 64 MiB on Android, however nothing seems to rely on this value anyway, as checked be grepping relevant code in drm_gralloc and Mesa. Cc: Rob Herring <rob.herring@linaro.org> Signed-off-by: Tomasz Figa <tfiga@google.com> [Emil Velikov: rebase against master. add missing __func__, Eric] Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Acked-by: John Stultz <john.stultz@linaro.org>
* meson,configure: include config.h automaticallyEric Engestrom2018-03-207-28/+0
| | | | | | | | | This will prevent any more missing `#include "config.h"` bug, at the cost of having to recompile some files that didn't need to be when changing build options. Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
* meson,configure: always define HAVE_OPEN_MEMSTREAMEric Engestrom2018-03-201-2/+2
| | | | | | Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
* libdrm: intel/Android.mk: Filter libdrm_intel library requirements on x86/x86_64John Stultz2018-03-181-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building AOSP after updating libdrm project to the freedesktop/master branch, I've seen the following build errors: external/libdrm/intel/Android.mk: error: libdrm_intel (SHARED_LIBRARIES android-arm64) missing libpciaccess (SHARED_LIBRARIES android-arm64) You can set ALLOW_MISSING_DEPENDENCIES=true in your environment if this is intentional, but that may defer real problems until later in the build. Using ALLOW_MISSING_DEPENDENCIES=true when building allows things to function properly, but is not ideal. So basically, while I'm not including the libdrm_intel package into the build, just the fact that the Android.mk file references libpciaccess which isn't a repo included in AOSP causes the build failure. So it seems we need some sort of conditional filter in the Android.mk to skip over it if we're not building for intel. Cc: Chad Versace <chad.versace@linux.intel.com> Cc: Marissa Wall <marissaw@google.com> Cc: Sean Paul <seanpaul@google.com> Cc: Dan Willemsen <dwillemsen@google.com> Cc: Tomasz Figa <tfiga@google.com> Cc: Robert Foss <robert.foss@collabora.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org>
* meson: use pkg-config to detect libatomic_opsEric Engestrom2018-03-091-1/+1
| | | | | Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
* intel/intel_chipset.h: Sync Cannonlake IDs.Rodrigo Vivi2018-03-051-24/+28
| | | | | | | | | | | | | | Let's sync CNL ids with Spec and kernel. Sync with kernel commit '3f43031b1693 ("drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.")' and commit 'e3890d05b342 ("drm/i915/cnl: Sync PCI ID with Spec.")' Cc: James Ausmus <james.ausmus@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
* *-symbol-check: Don't hard-code nm executableHeiko Becker2018-02-232-1/+2
| | | | | | | | | | | | Helpful if your nm executable has a prefix based on the architecture, for example. Signed-off-by: Heiko Becker <heirecka@exherbo.org> Cc: Timo Gurr <timo.gurr@gmail.com> [Eric: v2: rebase and add Meson support] Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
* always define HAVE_VALGRINDEric Engestrom2018-01-291-2/+2
| | | | | | Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
* Add meson build systemDylan Baker2018-01-121-0/+105
| | | | | | | | | | This patch adds a complete meson build system, including tests and install. It has the necessary hooks to allow it be used as a subproject for other meson based builds such as mesa. Signed-off-by: Dylan Baker <dylan.c.baker@intel.com> Reviewed-and-tested-by: Igor Gnatenko <i.gnatenko.brain@gmail.com> Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
* intel: Add more Coffeelake PCI IDsAnuj Phogat2018-01-111-7/+23
| | | | | | | | Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
* intel: Change a KBL pci id to GT2 from GT1.5Anuj Phogat2017-09-211-2/+2
| | | | | | | | | | See Mesa commit 9c588ff Cc: Matt Turner <mattst88@gmail.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
* intel/intel_chipset: Move IS_9XX below IS_GEN10.Rodrigo Vivi2017-06-301-9/+9
| | | | | | | | | | | | No functional change. Just organizing the code so it gets clear for future platforms. Paulo deserves credits becuase he was the one that just noticed this IS_9XX was in the wrong position after CNL patches got introduced. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
* intel: add GEN10 to IS_9XX.Paulo Zanoni2017-06-301-1/+2
| | | | | | | As far as I understand, IS_9XX should return true for it. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
* intel/gen10: Add missed gen10 stuffBen Widawsky2017-06-302-1/+5
| | | | | | | This got lost on rebase, I believe Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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