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authorJammy Zhou <Jammy.Zhou@amd.com>2015-05-29 12:59:59 +0200
committerAlex Deucher <alexander.deucher@amd.com>2015-08-05 13:47:50 -0400
commit40c53360437fec5faee83f0b64bb6756926d2fe0 (patch)
tree8b6a890d59082799ce18369ab00c9a0d12244189 /amdgpu/amdgpu_internal.h
parentef9aa370bb3a5e1725998a4b31237ffc14a062b0 (diff)
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amdgpu: get rid of IB pool management v3
v1: by Jammy Zhou v2: remove bo wait when destroy IB by Jammy Zhou v3: more cleanups by Marek Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
Diffstat (limited to 'amdgpu/amdgpu_internal.h')
-rw-r--r--amdgpu/amdgpu_internal.h20
1 files changed, 1 insertions, 19 deletions
diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h
index c1cd4da7..e5a457ab 100644
--- a/amdgpu/amdgpu_internal.h
+++ b/amdgpu/amdgpu_internal.h
@@ -97,42 +97,24 @@ struct amdgpu_bo_list {
uint32_t handle;
};
-/*
- * There are three mutexes.
- * To avoid deadlock, only hold the mutexes in this order:
- * sequence_mutex -> pendings_mutex -> pool_mutex.
-*/
struct amdgpu_context {
struct amdgpu_device *dev;
/** Mutex for accessing fences and to maintain command submissions
- and pending lists in good sequence. */
+ in good sequence. */
pthread_mutex_t sequence_mutex;
/** Buffer for user fences */
struct amdgpu_ib *fence_ib;
/** The newest expired fence for the ring of the ip blocks. */
uint64_t expired_fences[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS];
- /** Mutex for accessing pendings list. */
- pthread_mutex_t pendings_mutex;
- /** Pending IBs. */
- struct list_head pendings[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS];
- /** Freed IBs not yet in pool */
- struct list_head freed;
- /** Mutex for accessing free ib pool. */
- pthread_mutex_t pool_mutex;
- /** Internal free IB pools. */
- struct list_head ib_pools[AMDGPU_CS_IB_SIZE_NUM];
/* context id*/
uint32_t id;
};
struct amdgpu_ib {
amdgpu_context_handle context;
- struct list_head list_node;
amdgpu_bo_handle buf_handle;
void *cpu;
uint64_t virtual_mc_base_address;
- enum amdgpu_cs_ib_size ib_size;
- uint64_t cs_handle;
};
/**