Add definitions for store barrier.

I usually call this a "store/store barrier" for maximum clarity, but
the common way of describing it is "store barrier" or "store fence".

This doesn't use "dmb st" yet since we're waiting on the toolchain
update, but it gets the various macros and inline functions in place
so we can use them in the VM.

Bug 3003477

git cherry-pick 2ba5eec3972b4ce46feb677116534fcd3d136e0a

Change-Id: Ifd2d3588be96aa529d490789436cf48c962021ba

3 files changed, 33 insertions, 3 deletions

diff --git a/include/cutils/atomic-arm.h b/include/cutils/atomic-arm.h
index 0dd629d8..3ed9af24 100644
--- a/include/cutils/atomic-arm.h
+++ b/include/cutils/atomic-arm.h
@@ -28,18 +28,30 @@ extern inline void android_compiler_barrier(void)
 #if ANDROID_SMP == 0
 extern inline void android_memory_barrier(void)
 {
-  android_compiler_barrier();
+    android_compiler_barrier();
+}
+extern inline void android_memory_store_barrier(void)
+{
+    android_compiler_barrier();
 }
 #elif defined(__ARM_HAVE_DMB)
 extern inline void android_memory_barrier(void)
 {
     __asm__ __volatile__ ("dmb" : : : "memory");
 }
+extern inline void android_memory_store_barrier(void)
+{
+    /* TODO: use "dmb st" once the toolchain understands it */
+    __asm__ __volatile__ ("dmb" : : : "memory");
+}
 #elif defined(__ARM_HAVE_LDREX_STREX)
 extern inline void android_memory_barrier(void)
 {
-    __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5"
-                          : : "r" (0) : "memory");
+    __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0) : "memory");
+}
+extern inline void android_memory_store_barrier(void)
+{
+    android_memory_barrier();
 }
 #else
 extern inline void android_memory_barrier(void)
@@ -47,6 +59,10 @@ extern inline void android_memory_barrier(void)
     typedef void (kuser_memory_barrier)(void);
     (*(kuser_memory_barrier *)0xffff0fa0)();
 }
+extern inline void android_memory_store_barrier(void)
+{
+    android_memory_barrier();
+}
 #endif
 
 extern inline int32_t android_atomic_acquire_load(volatile int32_t *ptr)
diff --git a/include/cutils/atomic-inline.h b/include/cutils/atomic-inline.h
index 715e0aad..6acb67cf 100644
--- a/include/cutils/atomic-inline.h
+++ b/include/cutils/atomic-inline.h
@@ -55,4 +55,10 @@
 #define ANDROID_MEMBAR_FULL android_memory_barrier
 #endif
 
+#if ANDROID_SMP == 0
+#define ANDROID_MEMBAR_STORE android_compiler_barrier
+#else
+#define ANDROID_MEMBAR_STORE android_memory_store_barrier
+#endif
+
 #endif /* ANDROID_CUTILS_ATOMIC_INLINE_H */
diff --git a/include/cutils/atomic-x86.h b/include/cutils/atomic-x86.h
index 06b643fb..834379dc 100644
--- a/include/cutils/atomic-x86.h
+++ b/include/cutils/atomic-x86.h
@@ -29,11 +29,19 @@ extern inline void android_memory_barrier(void)
 {
     android_compiler_barrier();
 }
+extern inline void android_memory_store_barrier(void)
+{
+    android_compiler_barrier();
+}
 #else
 extern inline void android_memory_barrier(void)
 {
     __asm__ __volatile__ ("mfence" : : : "memory");
 }
+extern inline void android_memory_store_barrier(void)
+{
+    android_compiler_barrier();
+}
 #endif
 
 extern inline int32_t android_atomic_acquire_load(volatile int32_t *ptr) {